Patents by Inventor Naseer Babu PAZHEDAN

Naseer Babu PAZHEDAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with reduced poly spacing effect
    Patent number: 9704881
    Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate electrode over the semiconductor layer, forming a second gate electrode over the semiconductor layer, forming a mask layer between the first and second gate electrodes, etching a cavity into the semiconductor layer between the first and second gate electrodes using the mask layer as an etching mask, and forming a semiconductor material in the etched cavities.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Naseer Babu Pazhedan
  • SEMICONDUCTOR DEVICE WITH REDUCED POLY SPACING EFFECT
    Publication number: 20170084629
    Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate electrode over the semiconductor layer, forming a second gate electrode over the semiconductor layer, forming a mask layer between the first and second gate electrodes, etching a cavity into the semiconductor layer between the first and second gate electrodes using the mask layer as an etching mask, and forming a semiconductor material in the etched cavities.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Inventor: Naseer Babu Pazhedan
  • Integrated circuits having a metal gate structure and methods for fabricating the same
    Patent number: 9337296
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of a hafnium oxide material and a layer of hafnium silicate material. The layer of the hafnium silicate material includes less than about 40 % of an overall height of the gate insulation layer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Naseer Babu Pazhedan
  • INTEGRATED CIRCUITS HAVING A METAL GATE STRUCTURE AND METHODS FOR FABRICATING THE SAME
    Publication number: 20150021714
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of a hafnium oxide material and a layer of hafnium silicate material. The layer of the hafnium silicate material includes less than about 40% of an overall height of the gate insulation layer.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventor: Naseer Babu PAZHEDAN