Patents by Inventor Naser Alijabbari

Naser Alijabbari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10425040
    Abstract: An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 24, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens
  • Patent number: 10297707
    Abstract: A photovoltaic structure for absorption from the solar spectrum, includes a light transmitting substrate layer, a transparent electrode layer on the substrate layer, a direct band-gap, wide band-gap, nanocrystalline or microcrystalline, think film semiconducting first layer on the transparent electrode layer, a second think film layer comprising a narrow band-gap semiconductor on the first layer a second electrode layer on the second think film layer, and a protective layer on the second electrode layer. The structure has a hetero-structure at the boundary between the wide-band-gap layer and the second thin film layer. The second layer can be chalcogenide salt having an average thickness of 0.4 to 1.2 ?m, and preferably an average thickness of 0.5 to 0.6 ?m. The chalcogenide salt layer is a lead chalcogenide, such as a nanocrystaline lead sulfide, nanocrystalline lead selenide, or a nanocrystalline lead telluride.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 21, 2019
    Inventors: Tatiana Globus, Pineas Paxton Marshall, Boris Gelmont, Lloyd Harriott, Naser Alijabbari, John C Bean, Joe C Campbell
  • Patent number: 10283363
    Abstract: A quasi-vertical Schottky diode architecture includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin mesa of semiconductor material with epilayers including a bottomside highly-doped layer, a bottomside ohmic contact directly below the anode, and a host substrate onto which the diode material is bonded by a thin adhesive layer. A method of fabricating the diode architecture includes preparation of the semiconductor wafer for processing (including initial etching to expose the highly-doped epilayer, deposition of metals and annealing to form the ohmic contact, application of the adhesive layer to the host substrate, thermal compression bonding of diode wafer and host wafer, with ohmic contact side facing host wafer to form a composite wafer, etching and formation of diode mesas to isolate devices on the host substrate, lithography and formation of topside anode contact and external circuitry on host wafer).
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 7, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens
  • Publication number: 20170288607
    Abstract: An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi-vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.
    Type: Application
    Filed: August 28, 2015
    Publication date: October 5, 2017
    Applicant: University of Virginia
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens
  • Publication number: 20170250083
    Abstract: A quasi-vertical Schottky diode architecture includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin mesa of semiconductor material with epilayers including a bottomside highly-doped layer, a bottomside ohmic contact directly below the anode, and a host substrate onto which the diode material is bonded by a thin adhesive layer. A method of fabricating the diode architecture includes preparation of the semiconductor wafer for processing (including initial etching to expose the highly-doped epilayer, deposition of metals and annealing to form the ohmic contact, application of the adhesive layer to the host substrate, thermal compression bonding of diode wafer and host wafer, with ohmic contact side facing host wafer to form a composite wafer, etching and formation of diode mesas to isolate devices on the host substrate, lithography and formation of topside anode contact and external circuitry on host wafer).
    Type: Application
    Filed: August 28, 2015
    Publication date: August 31, 2017
    Applicant: UNIVERSITY OF VIRGINIA
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens