Patents by Inventor Naser Awad

Naser Awad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing verification method employing dynamic abstraction in core/shell partitioning
    Patent number: 6622290
    Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: September 16, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Mark Steven Hahn, Harish Kriplani, Naser Awad