Abstract: A method for improving wafer-level optical characteristic uniformity. The method includes forming a first layer of dielectric overlying the first wafer and a second layer of dielectric overlying the second wafer. The method also includes measuring a refractive index distribution of the second layer and measuring a first thickness distribution of the first layer. The method also includes determining a second thickness distribution for the first layer based on the refractive index distribution and the first thickness distribution. The method further includes removing material nonuniformly and selectively from the first layer based on the second thickness distribution, resulting in a third layer in the second thickness distribution characterized by a spectral response with a characteristic wavelength uniformity better than +/?2.5 nm across the first wafer.

Abstract: An optical coupler configured to couple light along a propagation direction is disclosed. The optical coupler includes a lower area. The lower area includes a waveguide including a first end, a second end, and an inversely tapered portion. The optical coupler includes an intermediary area arranged over, in a vertical direction, the lower area. The intermediary area includes two or more intermediary elements. The optical coupler includes an upper area arranged over the intermediary area. The upper area includes one or more upper elements.

Abstract: A fabrication-tolerant non-linear waveguide taper for a waveguide transition can be designed by computing the scattering rate associated with the waveguide transition as a function of waveguide width of the waveguide taper for each of multiple sets of parameter values characterizing the waveguide transition (e.g., a set of nominal parameter values and sets of parameter values associated with process corners representing process variations from the nominal parameter values), determining an envelope of the computed width-dependent scattering rates, and computing a non-linear taper profile of the waveguide taper based on the envelope.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.

Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.

Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.