Patents by Inventor Naser Dalvand

Naser Dalvand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240036263
    Abstract: An optical coupler configured to couple light along a propagation direction is disclosed. The optical coupler includes a lower area. The lower area includes a waveguide including a first end, a second end, and an inversely tapered portion. The optical coupler includes an intermediary area arranged over, in a vertical direction, the lower area. The intermediary area includes two or more intermediary elements. The optical coupler includes an upper area arranged over the intermediary area. The upper area includes one or more upper elements.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicants: Broadcom International Pte. Ltd., Broadcom International Pte. Ltd.
    Inventors: Nourhan Eid, Shiyun Lin, Naser Dalvand, Vivek Raghunathan
  • Patent number: 11215758
    Abstract: A fabrication-tolerant non-linear waveguide taper for a waveguide transition can be designed by computing the scattering rate associated with the waveguide transition as a function of waveguide width of the waveguide taper for each of multiple sets of parameter values characterizing the waveguide transition (e.g., a set of nominal parameter values and sets of parameter values associated with process corners representing process variations from the nominal parameter values), determining an envelope of the computed width-dependent scattering rates, and computing a non-linear taper profile of the waveguide taper based on the envelope.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 4, 2022
    Assignee: Juniper Networks, Inc.
    Inventors: Naser Dalvand, Erik Johan Norberg
  • Publication number: 20210225732
    Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Erik Johan Norberg, Naser Dalvand, Gregory Alan Fish
  • Patent number: 10998252
    Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 4, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: Erik Johan Norberg, Naser Dalvand, Gregory Alan Fish
  • Publication number: 20200211923
    Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
    Type: Application
    Filed: February 14, 2020
    Publication date: July 2, 2020
    Inventors: Erik Johan Norberg, Naser Dalvand, Gregory Alan Fish
  • Patent number: 10651110
    Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 12, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Erik Johan Norberg, Naser Dalvand, Gregory Alan Fish
  • Publication number: 20200044746
    Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Naser Dalvand, Erik Johan Borberg, Brian Robert Kock
  • Patent number: 10498460
    Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: December 3, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Naser Dalvand, Erik Johan Norberg, Brian Robert Koch
  • Publication number: 20190273563
    Abstract: Described are various configurations for an amplifying optical demultiplexer. Various embodiments can receive an input signal comprising multiple sub-signals, and separate and amplify the signals within the demultiplexer. Some embodiments include a multistage demultiplexer with amplifiers located between a first and second stage. Some embodiments include a multistage demultiplexer with amplifiers located between a second and third stage.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Naser Dalvand, Erik Johan Norberg, Brian Robert Koch