Abstract: A system and method for limiting fixed pattern noise (FPN) in a time delay and integration (TDI) mode of operation of a complementary metal oxide semiconductor (CMOS) imaging device is disclosed. The system and method provide for each line time, selecting a pixel for each column of photosensitive elements in the along track direction to capture dark information such that the selected pixel does not correspond to a portion of a scene that was previously selected to capture dark information in a current TDI period. The dark information for the selected pixels is captured and summed for each column of photosensitive elements. This sum is then used during a next TDI time period to subtract FPN effects from the output of the corresponding column. This allows the dark sum information to be constantly updated while the image sensor is in use while only decreasing the responsitivity by (N?1)/N relative to an N pixel column of a traditional TDI operation.

Abstract: A CMOS time delay and integration image sensor is disclosed having analog sampling stages coupled to the column bus that correspond to a pixel in the column. The analog sampling stages have a first memory element that stores the pixels reset level signal and a second memory element that stores an output signal of a previous analog sampling stage in the column. The analog sampling stage integrates the signal of the previous analog sampling stage with the sampled photosignal of the corresponding pixel and subtracts the reset level. The analog sampling stage architecture provides global shuttering and correlated double sampling and only requires a single analog to digital conversion for each TDI line time.

Abstract: A CMOS time delay and integration image sensor is disclosed having analog sampling stages coupled to the column bus that correspond to a pixel in the column. The analog sampling stages have a first memory element that stores the pixels reset level signal and a second memory element that stores an output signal of a previous analog sampling stage in the column. The analog sampling stage integrates the signal of the previous analog sampling stage with the sampled photosignal of the corresponding pixel and subtracts the reset level. The analog sampling stage architecture provides global shuttering and correlated double sampling and only requires a single analog to digital conversion for each TDI line time.