Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract: A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block with a dummy bit line connected to the dummy column and to a timing circuit. A normal bit line connected to the normal memory cells provides the read normal bit to input/output logic. Whenever a normal memory cell is accessed during the read operation, the circuitry of the corresponding dummy row enables the dummy bit line to discharge, and when the voltage across the dummy bit line reaches a predetermined value, the timing circuit produces a timing signal to activate the input/output circuitry to read the data stored in the accessed memory cell.

Abstract: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics.

Abstract: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation.

Abstract: A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block with a dummy bit line connected to the dummy column and to a timing circuit. A normal bit line connected to the normal memory cells provides the read normal bit to input/output logic. Whenever a normal memory cell is accessed during the read operation, the circuitry of the corresponding dummy row enables the dummy bit line to discharge, and when the voltage across the dummy bit line reaches a predetermined value, the timing circuit produces a timing signal to activate the input/output circuitry to read the data stored in the accessed memory cell.

Abstract: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation.

Abstract: An improved semiconductor memory device providing row/column redundancy. The device includes a plurality of data latches arranged in a row-column matrix connected to a set of bitlines/global bitlines interfacing to read/write circuitry, at least two redundant row/column connected to a redundant bitline/global bitline, a first device for providing a first faulty row/column address in said matrix, a second device for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means, a comparison circuitry receiving as its inputs the accessed row/column address and the faulty row/column addresses, and a control block connected to the said comparison circuitry that receives a control signal such that it enables/disables the redundant and/or other memory cell row/column depending upon signals received from said comparison circuitry and control signal for normal operation of the memory device.

Abstract: An improved semiconductor memory device providing row/column redundancy. The device includes a plurality of data latches arranged in a row-column matrix connected to a set of bitlines/global bitlines interfacing to read/write circuitry, at least two redundant row/column connected to a redundant bitline/global bitline, a first device for providing a first faulty row/column address in said matrix, a second device for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means, a comparison circuitry receiving as its inputs the accessed row/column address and the faulty row/column addresses, and a control block connected to the said comparison circuitry that receives a control signal such that it enables/disables the redundant and/or other memory cell row/column depending upon signals received from said comparison circuitry and control signal for normal operation of the memory device.