Patents by Inventor Nasr-Eddine Walehiane

Nasr-Eddine Walehiane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6845504
    Abstract: A system and method for efficiently managing lock contention for a central processing unit (CPU) of a computer system. The present invention uses both spinning and blocking (or undispatching) to manage threads when they are waiting to acquire a lock. In addition, the present invention intelligently determines when the program thread should spin and when the program thread should become undispatched. If it is determined that the program thread should become undispatched, the present invention provides efficient undispatching of program threads that improves throughput by reducing wait time to acquire the lock.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: January 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Hong L. Hua, Bret R. Olszewski, Mysore S. Srinivas, Nasr-Eddine Walehiane
  • Patent number: 6711644
    Abstract: An apparatus and method for communicating the completion of asynchronous I/O requests is provided. In particular, the apparatus and method make use of a new function call which is capable of waiting for a predetermined number of I/O requests to be completed prior to returning to the calling application. Control blocks for the I/O requests are updated after a predetermined number of I/O requests have been completed, i.e. in a process context rather than in an interrupt context as in the known systems. In this way, the overhead associated with known asynchronous I/O system calls is reduced.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Kumar V. Nallapati, Mysore Sathyanaraya Srinivas, James William VanFleet, Nasr-Eddine Walehiane, Michael William Wortman
  • Patent number: 6477597
    Abstract: The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a first lock state indicates that said resource is free. The requesting processor is placed on active standby if a second lock state indicates that said resource is busy. A lock includes a first and second lock state. The first lock state corresponds to a null value, and the second lock state corresponds to a non-null value.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 5, 2002
    Assignee: Bull, S.A.
    Inventors: Jean-Dominique Sorace, Nasr-Eddine Walehiane
  • Publication number: 20020107854
    Abstract: A system and method for efficiently managing lock contention for a central processing unit (CPU) of a computer system. The present invention uses both spinning and blocking (or undispatching) to manage threads when they are waiting to acquire a lock. In addition, the present invention intelligently determines when the program thread should spin and when the program thread should become undispatched. If it is determined that the program thread should become undispatched, the present invention provides efficient undispatching of program threads that improves throughput by reducing wait time to acquire the lock.
    Type: Application
    Filed: February 8, 2001
    Publication date: August 8, 2002
    Applicant: Internaional Business Machines Corporation
    Inventors: Hong L. Hua, Bret R. Olszewski, Mysore S. Srinivas, Nasr-Eddine Walehiane
  • Patent number: 6073247
    Abstract: The invention relates to a process for synchronizing a computer system with regard to a date which changes over time. The computer system comprises one or more modules (1, 2, 3, 4), each module (1, 2) comprising several processors (10, 11, 12, 13, 20, 21, 22, 23) regulated by a clock specific to a module (1, 2). Each processor (10, 11, 12, 13, 20, 21, 22, 23) comprises a private register TBR (16, 17, 18, 19, 26, 27, 28, 29) adapted to contain a value corresponding to said date and to undergo an incrementation by the clock specific to the module (1, 2) comprising this processor (10, 11, 12, 13, 20, 21, 22, 23).
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: June 6, 2000
    Assignee: BULL, S.A.
    Inventors: Michele Boutet, Nasr-Eddine Walehiane