Patents by Inventor Nasrin Jaffari

Nasrin Jaffari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9906195
    Abstract: An amplifier including: an input terminal coupled to a first node; an output terminal coupled to a second node; and a transistor coupled between a first power source and a second power source, the transistor including: a gate electrode coupled to the first node; a drain electrode coupled to the second node; a source electrode coupled to a third node; and a bulk electrode coupled to a fourth node and configured to receive a bulk voltage to change a threshold voltage of the transistor.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: February 27, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Patent number: 9746869
    Abstract: A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 29, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Patent number: 9614530
    Abstract: A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Publication number: 20160173098
    Abstract: A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.
    Type: Application
    Filed: October 7, 2015
    Publication date: June 16, 2016
    Inventor: Nasrin Jaffari
  • Publication number: 20160164475
    Abstract: An amplifier including: an input terminal coupled to a first node; an output terminal coupled to a second node; and a transistor coupled between a first power source and a second power source, the transistor including: a gate electrode coupled to the first node; a drain electrode coupled to the second node; a source electrode coupled to a third node; and a bulk electrode coupled to a fourth node and configured to receive a bulk voltage to change a threshold voltage of the transistor.
    Type: Application
    Filed: November 19, 2015
    Publication date: June 9, 2016
    Inventor: Nasrin JAFFARI
  • Patent number: 9294039
    Abstract: A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: March 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Patent number: 9197395
    Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: November 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amir Amirkhany, Nasrin Jaffari
  • Patent number: 9100017
    Abstract: An impedance circuit coupled to a first power supply includes: an output node; a transistor coupled between the output node and the first power supply, wherein the transistor comprises a gate electrode; and a voltage source electrically coupled to the gate electrode of the transistor and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source includes: a plurality of impedance components electrically coupled in series between a circuit node and the first power supply, and a current source electrically coupled between the circuit node and a second power supply.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: August 4, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Patent number: 9094077
    Abstract: A receiver for receiving digital data after transmission through a channel which produces inter-symbol interference or other distortion. In one embodiment, a received signal is differentiated before being digitized to form an output digital bit stream, to reduce the effects of inter-symbol interference and other distortion in the channel. The differentiated signal is compared to two threshold values, a first threshold value, and a second threshold value, the first threshold value being greater than the second threshold value. When the differentiated signal exceeds the first threshold, the output bit is 1, when the differentiated signal is less than the second threshold value, the output bit is 0, and when the differentiated signal is between the first threshold value and the second threshold value, the output bit is the same as the previous output bit.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Publication number: 20150160679
    Abstract: A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.
    Type: Application
    Filed: November 19, 2014
    Publication date: June 11, 2015
    Inventor: Nasrin Jaffari
  • Publication number: 20150054586
    Abstract: A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.
    Type: Application
    Filed: February 13, 2014
    Publication date: February 26, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Publication number: 20150016580
    Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
    Type: Application
    Filed: August 21, 2014
    Publication date: January 15, 2015
    Inventors: Amir Amirkhany, Nasrin Jaffari
  • Publication number: 20150015326
    Abstract: A bulk-modulated current source includes: an output terminal configured to supply an output current; a first transistor comprising: a first electrode coupled to the output terminal, a second electrode, a bulk electrode, and a gate electrode configured to receive a bias voltage; and an amplifier comprising: an input terminal electrically coupled to the first electrode of the first transistor, and an output terminal electrically coupled to the bulk electrode of the first transistor.
    Type: Application
    Filed: April 22, 2014
    Publication date: January 15, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nasrin Jaffari
  • Publication number: 20150008965
    Abstract: An impedance circuit coupled to a first power supply includes: an output node; a transistor coupled between the output node and the first power supply, wherein the transistor comprises a gate electrode; and a voltage source electrically coupled to the gate electrode of the transistor and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source includes: a plurality of impedance components electrically coupled in series between a circuit node and the first power supply, and a current source electrically coupled between the circuit node and a second power supply.
    Type: Application
    Filed: February 13, 2014
    Publication date: January 8, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Publication number: 20140294129
    Abstract: A receiver for receiving digital data after transmission through a channel which produces inter-symbol interference or other distortion. In one embodiment, a received signal is differentiated before being digitized to form an output digital bit stream, to reduce the effects of inter-symbol interference and other distortion in the channel. The differentiated signal is compared to two threshold values, a first threshold value, and a second threshold value, the first threshold value being greater than the second threshold value. When the differentiated signal exceeds the first threshold, the output bit is 1, when the differentiated signal is less than the second threshold value, the output bit is 0, and when the differentiated signal is between the first threshold value and the second threshold value, the output bit is the same as the previous output bit.
    Type: Application
    Filed: August 7, 2013
    Publication date: October 2, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nasrin Jaffari
  • Patent number: 8836411
    Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
  • Patent number: 8817184
    Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: August 26, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amir Amirkhany, Nasrin Jaffari
  • Patent number: 8674749
    Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: March 18, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu AAron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
  • Patent number: 8497667
    Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
  • Publication number: 20130187707
    Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
    Type: Application
    Filed: December 24, 2012
    Publication date: July 25, 2013
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly