Abstract: An interrupt service table pointer (ISTP) facilitates fast branching to interrupt service routines. An interrupt service table base (ISTB) field establishes a base address at which one or more routines reside in memory. A highest priority enabled interrupt (HPEINT) field identifies an interrupt to service. The concatenation of the ISTB, the HPEINT, and one or more least significant zeros points to the first instruction of a group of instructions which service a specific interrupt. The ISTB is user programmable. The HPEINT is automatically calculated each cycle by the data processor incorporating the ISTP.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Abstract: The invention provides a method for interrupting processing by a processor. The method includes the step of requesting an analysis interrupt by setting a bit in a register in the processor (119), the bit associated with an analysis interrupt, the analysis interrupt having a configurable priority. The method also includes the step of detecting the analysis interrupt request. The method further comprises assigning an assigned priority level (114) to the analysis interrupt from a range of priority levels and processing the analysis interrupt (124) based on the assigned priority level.The invention also provides a processor having a memory unit (14, 16) and a central processing unit (12) operable to access the memory unit. The central processing unit (12) includes an interrupt priority parameter storage system (80) for storing an interrupt priority parameter.