Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.