Patents by Inventor Natalia Borjemscaia

Natalia Borjemscaia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field-effect transistors with self-aligned and non-self-aligned contact openings
    Patent number: 10833160
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
  • FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED AND NON-SELF-ALIGNED CONTACT OPENINGS
    Publication number: 20200335591
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
  • Corrosion resistant chip sidewall connection with crackstop and hermetic seal
    Patent number: 9852959
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fitzsimmons, Michael J. Shapiro, Natalia Borjemscaia, Vincent McGahay
  • Electrical connection around a crackstop structure
    Patent number: 9812404
    Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Michael J. Shapiro, John A. Fitzsimmons, Natalia Borjemscaia
  • CORROSION RESISTANT CHIP SIDEWALL CONNECTION WITH CRACKSTOP AND HERMETIC SEAL
    Publication number: 20170229362
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: John A. Fitzsimmons, Michael J. Shapiro, Natalia Borjemscaia, Vincent McGahay
  • ELECTRICAL CONNECTION AROUND A CRACKSTOP STRUCTURE
    Publication number: 20170194265
    Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Michael J. Shapiro, John A. Fitzsimmons, Natalia Borjemscaia