Patents by Inventor Nataliya Yakimets

Nataliya Yakimets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8742789
    Abstract: An interconnected array of reconfigurable logic cells which carry out at least one logic function, externally connected to peripheral connection network equipped with switch boxes and connected to programmable input/output blocks. The logic cells are distributed in a first dimension in rows i with i=1 to d and a second dimension in columns j with j=1 to w, with d?2 and w=2 or d=2 and w?2, each logic cell including a second input, a second input, a first output and a second output, the first input of each logic cell and the first output of each logic cell being connected to the connection network, the second input and the second output of each logic cell being connected to other different column and row logic cells except for the first and last rows or columns for d>2 or w>2 respectively.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 3, 2014
    Assignees: Ecole Centrale de Lyon, Universite Claude Bernard, Centre National de la Recherche Scientfique, Institut National des Sciences Appliquees de Lyon
    Inventors: Ian O'Connor, Nataliya Yakimets
  • Publication number: 20120326749
    Abstract: An interconnected array of reconfigurable logic cells which carry out at least one logic function, externally connected to peripheral connection network equipped with switch boxes and connected to programmable input/output blocks. The logic cells are distributed in a first dimension in rows i with i=1 to d and a second dimension in columns j with j=1 to w, with d?2 and w=2 or d=2 and w?2, each logic cell including a second input, a second input, a first output and a second output, the first input of each logic cell and the first output of each logic cell being connected to the connection network, the second input and the second output of each logic cell being connected to other different column and row logic cells except for the first and last rows or columns for d>2 or w>2 respectively.
    Type: Application
    Filed: December 14, 2010
    Publication date: December 27, 2012
    Applicants: ECOLE CENTRALE DE LYON, INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE CLAUDE BERNARD LYON I
    Inventors: Ian O'Connor, Nataliya Yakimets