Patents by Inventor Natalya BONDARENKO
Natalya BONDARENKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126458Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Inventors: Stefano GHIGGINI, Natalya Bondarenko, Luca NASSI, Geoffray Matthieu LACOURBA, Huzefa Moiz SANJELIWALA, Miles Robert DOOLEY, . ABHISHEK RAJA
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Patent number: 11853220Abstract: An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.Type: GrantFiled: October 14, 2021Date of Patent: December 26, 2023Assignee: Arm LimitedInventors: Natalya Bondarenko, Stefano Ghiggini, Damien Matthieu Valentin Cathrine, Ugo Castorina
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Publication number: 20230121686Abstract: An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.Type: ApplicationFiled: October 14, 2021Publication date: April 20, 2023Inventors: Natalya BONDARENKO, Stefano GHIGGINI, Damien Matthieu Valentin CATHRINE, Ugo CASTORINA
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Patent number: 11580032Abstract: A technique is provided for training a prediction apparatus. The apparatus has an input interface for receiving a sequence of training events indicative of program instructions, and identifier value generation circuitry for performing an identifier value generation function to generate, for a given training event received at the input interface, an identifier value for that given training event. The identifier value generation function is arranged such that the generated identifier value is dependent on at least one register referenced by a program instruction indicated by that given training event. Prediction storage is provided with a plurality of training entries, where each training entry is allocated an identifier value as generated by the identifier value generation function, and is used to maintain training data derived from training events having that allocated identifier value.Type: GrantFiled: January 20, 2021Date of Patent: February 14, 2023Assignee: Arm LimitedInventors: Frederic Claude Marie Piry, Natalya Bondarenko, Cédric Denis Robert Airaud, Geoffray Matthieu Lacourba
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Publication number: 20230042247Abstract: A data processing apparatus comprises receiver circuitry for receiving instructions from each of a plurality of requester devices. Processing circuitry executes the instructions associated with each of a subset of the requester devices at a time and arbitration circuitry determines the subset of the requester devices and causes the instructions associated with each of the subset of the requester devices to be executed next. In response to the receiver circuitry receiving an instruction of a predetermined type from one of the requester devices outside the subset of requester devices, the arbitration circuitry causes the instruction of the predetermined type to be executed next.Type: ApplicationFiled: August 9, 2021Publication date: February 9, 2023Inventors: Frederic Claude Marie PIRY, Cédric Denis Robert AIRAUD, Natalya BONDARENKO, Luca MARONCELLI, Geoffray Matthieu LACOURBA
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Publication number: 20220308880Abstract: The invention provides a data processing apparatus and a data processing method for generating prefetches of data for use during execution of instructions by processing circuitry. The prefetches that are generated are based on a nested prefetch pattern. The nested prefetch pattern comprises a first pattern and a second pattern. The first pattern is defined by a first address offset between sequentially accessed addresses and a first observed number of the sequentially accessed addresses separated by the first address offset. The second pattern is defined by a second address offset between sequential iterations of the first pattern and a second observed number of the sequential iterations of the first pattern separated by the second address offset.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Natalya BONDARENKO, Stefano GHIGGINI, Geoffray Matthieu LACOURBA, Cédric Denis Robert AIRAUD
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Publication number: 20220229783Abstract: A technique is provided for training a prediction apparatus. The apparatus has an input interface for receiving a sequence of training events indicative of program instructions, and identifier value generation circuitry for performing an identifier value generation function to generate, for a given training event received at the input interface, an identifier value for that given training event. The identifier value generation function is arranged such that the generated identifier value is dependent on at least one register referenced by a program instruction indicated by that given training event. Prediction storage is provided with a plurality of training entries, where each training entry is allocated an identifier value as generated by the identifier value generation function, and is used to maintain training data derived from training events having that allocated identifier value.Type: ApplicationFiled: January 20, 2021Publication date: July 21, 2022Inventors: Frederic Claude Marie PIRY, Natalya BONDARENKO, Cédric Denis Robert AIRAUD, Geoffray Matthieu LACOURBA
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Patent number: 11163691Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address.Type: GrantFiled: June 25, 2019Date of Patent: November 2, 2021Assignee: ARM LIMITEDInventors: Stefano Ghiggini, Natalya Bondarenko, Damien Guillaume Pierre Payet, Lucas Garcia
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Patent number: 11138119Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.Type: GrantFiled: January 15, 2019Date of Patent: October 5, 2021Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Natalya Bondarenko, Florent Begon, Lucas Garcia
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Patent number: 11086781Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.Type: GrantFiled: October 21, 2019Date of Patent: August 10, 2021Assignee: Arm LimitedInventors: Natalya Bondarenko, Florent Begon, Nathanael Premillieu, Pierre Marcel Laurent
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Patent number: 10956206Abstract: A technique is described for managing a cache structure in a system employing transactional memory. The apparatus comprises processing circuitry to perform data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction, and a cache structure comprising a plurality of cache entries for storing data for access by the processing circuitry. Each cache entry has associated therewith an allocation tag, and allocation tag control circuitry is provided to control use of a plurality of allocation tags and to maintain an indication of a current state of each of those allocation tags.Type: GrantFiled: April 2, 2019Date of Patent: March 23, 2021Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Lucas Garcia, Natalya Bondarenko, Stefano Ghiggini
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Patent number: 10783031Abstract: An apparatus comprises processing circuitry, transactional memory support circuitry and a cache. The processing circuitry processes threads of data processing, and the transactional memory support circuitry supports execution of a transaction within a thread, including tracking a read set of addresses, comprising addresses accessed by read instructions within the transaction. A transaction comprises instructions for which the processing circuitry is configured to prevent commitment of the results of speculatively executed instruction until the transaction has completed. The cache has a plurality of entries, each associated with an address and specifying a replaceable-information value for that address that comprises information for which, outside of the transaction, processing would be functionally correct even if the information was incorrect.Type: GrantFiled: August 20, 2018Date of Patent: September 22, 2020Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Lucas Garcia, Natalya Bondarenko, Stefano Ghiggini
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Patent number: 10776274Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesType: GrantFiled: March 2, 2018Date of Patent: September 15, 2020Assignee: Arm LimitedInventors: Lucas Garcia, Geoffray Matthieu Lacourba, Natalya Bondarenko, Nathanael Premillieu
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Patent number: 10769069Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whicType: GrantFiled: March 2, 2018Date of Patent: September 8, 2020Assignee: Arm LimitedInventors: Natalya Bondarenko, Lucas Garcia, Geoffray Matthieu Lacourba
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Publication number: 20200125492Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.Type: ApplicationFiled: October 21, 2019Publication date: April 23, 2020Inventors: Natalya BONDARENKO, Florent Begon, Nathanael Premillieu, Pierre Marcel Laurent
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Publication number: 20200065257Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address.Type: ApplicationFiled: June 25, 2019Publication date: February 27, 2020Inventors: Stefano GHIGGINI, Natalya BONDARENKO, Damien Guillaume Pierre PAYET, Lucas GARCIA
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Publication number: 20200057692Abstract: An apparatus comprises processing circuitry, transactional memory support circuitry and a cache. The processing circuitry processes threads of data processing, and the transactional memory support circuitry supports execution of a transaction within a thread, including tracking a read set of addresses, comprising addresses accessed by read instructions within the transaction. A transaction comprises instructions for which the processing circuitry is configured to prevent commitment of the results of speculatively executed instruction until the transaction has completed. The cache has a plurality of entries, each associated with an address and specifying a replaceable-information value for that address that comprises information for which, outside of the transaction, processing would be functionally correct even if the information was incorrect.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Damien Guillaume Pierre PAYET, Lucas GARCIA, Natalya BONDARENKO, Stefano GHIGGINI
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Publication number: 20190347124Abstract: A technique is described for managing a cache structure in a system employing transactional memory. The apparatus comprises processing circuitry to perform data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction, and a cache structure comprising a plurality of cache entries for storing data for access by the processing circuitry. Each cache entry has associated therewith an allocation tag, and allocation tag control circuitry is provided to control use of a plurality of allocation tags and to maintain an indication of a current state of each of those allocation tags.Type: ApplicationFiled: April 2, 2019Publication date: November 14, 2019Inventors: Damien Guillaume Pierre PAYET, Lucas GARCIA, Natalya BONDARENKO, Stefano GHIGGINI
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Publication number: 20190272233Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesType: ApplicationFiled: March 2, 2018Publication date: September 5, 2019Inventors: Lucas GARCIA, Geoffray Matthieu LACOURBA, Natalya BONDARENKO, Nathanael PREMILLIEU
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Publication number: 20190272234Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whicType: ApplicationFiled: March 2, 2018Publication date: September 5, 2019Inventors: Natalya BONDARENKO, Lucas GARCIA, Geoffray Matthieu LACOURBA