Abstract: The invention provides a method for providing an image, the method includes: exposing a first group of pixels located at a first location to light, during an intermediate exposure period, to provide analog signals representative of the light; and transferring the analog signals to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift; then further exposure of the second group of pixels etc.

Abstract: The invention provides a method and apparatus. The apparatus includes a pixels (10) adapted to receive light and to output a current representative of the received light; a feedback circuitry (20), connected to the pixel (10), adapted to receive said current and to receive a reference current (Iref) and to provide a feedback signal to the pixel (10) at least during at least a reset stage of the pixel (10). The method includes: (i) receiving light, by a pixel 10), and providing a pixel output signal representative of the received light; (ii) receiving, by a feedback circuitry, the pixel output signal; and (iii) providing multiple feedback signals to the pixel at least during a reset stage of the pixel (10).

Abstract: The invention provides a method for providing an image, the method includes: exposing a first group of pixels located at a first location to light, during an intermediate exposure period, to provide analog signals representative of the light; and transferring the analog signals to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift; then further exposure of the second group of pixels etc.

Abstract: The invention provides a method and apparatus. The apparatus includes a pixel (10) adapted to receive light and to output a current representative of the received light; a feedback circuitry (20), connected to the pixel (10), adapted to receive said current and to receive a reference current (Iref) and to provide a feedback signal to the pixel (10) at least during at least a reset stage of the pixel (10). The method includes: (i) receiving light, by a pixel 10), and providing a pixel output signal representative of the received light; (ii) receiving, by a feedback circuitry, the pixel output signal; and (iii) providing multiple feedback signals to the pixel at least during a reset stage of the pixel (10).

Abstract: The Viterbi algorithm (20) is performed with a reduced number of calculations when the comparing step (C, 80, 50) is anticipated before the selecting (S, 62, 64, 66, 68) and adding steps (A, 74, 76). During comparing (C), selection decisions (e.g., D (i)) are obtained by analyzing pairs of old path metrics (e.g., P (2i, j−1) at 91, P (2i+1, j−1) at 92) by subtracting and multiplying the path metrics with branch metrics (e.g., B (i, j) at 95) and combining intermediate sign (e.g., SP, SB, S&Dgr;) by e.g., and-logic (50). Selecting decisions (e.g., D (i/2, j+1), D (i/2+N/2, j+1) and new path metrics (e.g., P (i, j), P (i+12, j) are continuously stored and updated.

Abstract: The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.

Abstract: Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

Abstract: The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

Abstract: A parallel data structure and a dedicated Viterbi shift left instruction minimize the number of clock cycles required for decoding a convolutionally encoded signal in a data processing system (20) in software. Specifically, the data structure and Viterbi shift left instruction reduce the number of clock cycles required for performing an add-compare-select butterfly operation. The add-compare-select butterfly operation is included in a DO loop in a plurality of instructions for executing a Viterbi decoding algorithm, and is repeated a predetermined number of times, for choosing the best path through a trellis diagram.

Abstract: Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.

Abstract: To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.

Abstract: A crystal oscillator circuit having an accurate duty cycle at very high frequency is provided. An oscillator stage is provided which receives regenerative feedback from an inverter to sustain oscillation. The oscillator stage provides an AC output signal having a first average DC value determined by the regenerative feedback. The AC signal is coupled to a clipping circuit which symmetrically clips the AC signal about a predetermined second average DC level at first and second predetermined voltage levels. The inverter receives the clipped signal and provides an oscillating clock signal with an accurate duty cycle in response thereto.