Abstract: This application discloses a scanning electron microscope system to capture an image of an electronic device manufactured according to a layout design describing the electronic device, and a computing system to generate a predicted image of the electronic device using the layout design. The predicted image corresponds to an expected image of the electronic design system captured by the scanning electron microscope system. The computing system identifies manufacturing defects present in the electronic device based on differences between the predicted image of the electronic device and the captured image of the electronic device, and utilizes the captured image of the electronic device to classify the manufacturing defects identified based on the predicted image of the electronic device from the layout design. The computing system can generate a manufacturing defect report identifying the manufacturing defects used to perform repair of the electronic device or modification of the layout design.

Abstract: This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.

Abstract: A method and apparatus for inserting flip-flops in a circuit design between a driver and one or more receiver(s) comprising generating a candidate solution to assign the flip-flop at the node in the circuit, calculating a margin at the driver, calculating the margin at the receiver, and inserting the flip-flop at the node to simultaneously maximize the margin at the driver and the margin at the receiver. Furthermore, the method and apparatus determines whether to insert a second flip-flop at a second node in the circuit, and inserting the second flip-flop at the second node in the circuit such that a delay between the flip-flop and the second flip-flop is substantially equal to a clock period.

Abstract: A method and apparatus for inserting flip-flops in a circuit design between a driver and one or more receiver(s) comprising generating a candidate solution to assign the flip-flop at the node in the circuit, calculating a margin at the driver, calculating the margin at the receiver, and inserting the flip-flop at the node to simultaneously maximize the margin at the driver and the margin at the receiver. Furthermore, the method and apparatus determines whether to insert a second flip-flop at a second node in the circuit, and inserting the second flip-flop at the second node in the circuit such that a delay between the flip-flop and the second flip-flop is substantially equal to a clock period.

Abstract: The present invention beneficially provides a method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design. The printed circuit board design includes a cross-hatched fill area comprising boundary lines and cross-hatched lines within the boundary lines. Furthermore, the boundary lines and cross-hatched lines have a particular aperture. The printed circuit board design is automatically modified to fill partial hatch areas, if any, in the cross-hatched fill area. In one embodiment, the cross-hatched fill area is converted to a bit map of one dimensional edges representing the lines in the cross-hatched fill area. In this embodiment, partial hatch areas are identified based on the bit map, and edges are added in the identified partial hatch areas. Then, the embodiment converts the additional edges into corresponding lines in the printed circuit board design, wherein the lines have the particular aperture, to fill the partial hatch areas.