Patents by Inventor Natasha Healey

Natasha Healey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12672592
    Abstract: A current sensor integrated circuit (IC) package includes an insulation structure disposed between a semiconductor die and a lead frame to control gap height and prevent the die from tilting and dropping the magnetic field coupling between the die the primary conductor. An insulation structure is disposed between the die and the lead frame such that the die remains level and magnetic coupling remains intact. An insulation structure may control the gap height between the lead frame and the die evenly during transfer molding, by supporting the die across its length and/or width. Epoxy dots are also or instead used to control the gap height and eliminate die tilt.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: June 30, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: David Youm, Weidong Wang, Natasha Healey
  • Publication number: 20260023136
    Abstract: A current sensor integrated circuit (IC) package is flip-chip bonded using a conductive film to connect the IC circuit bond pads to the lead frame. A conductive film is positioned between the die surface of a semiconductor die and at least one signal lead of the lead frame. The conductive film is conductive in a first direction between the die and the signal lead and nonconductive in other directions. The conductive film is further configured to control a gap height between the die and the lead frame to reduce die tilt, thus improving the sensitivity and performance consistency of the package.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 22, 2026
    Applicant: Allegro MicroSystems, LLC
    Inventors: Weidong Wang, David Youm, Natasha Healey
  • Publication number: 20250364376
    Abstract: An integrated circuit package includes a lead frame with a split die-attach paddle (DAP) that supports a semiconductor die with one or more magnetic field sensing elements. The split paddle reduces magnetic reluctance for enhancing coupling to the die and reducing eddy currents. The package provides mechanical stability to prevent die tilt, limiting sensing errors and protecting the die from stress from downstream mechanical forces during test and assembly pick processes. The mechanical stability is provided by one or more leads, strip tie-bars and/or band bars.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 27, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Weidong Wang, Tonkla Faekrathok, Natasha Healey, Mongkolwattana Manoyot
  • Publication number: 20250309061
    Abstract: A magnetic field sensor comprises a die, first and second magnetic field sensing elements supported by the die, at respective spaced apart positions, and a lead frame supporting the die. The lead frame comprises a die attach segment having first and second openings formed therein, where there is no lead frame covering either magnetic field sensing element. The die attach segment includes a horizontal support portion disposed between the first and second openings, having a size configured to provide die support along a predetermined portion of at least one predetermined horizontal axis of the die. In other aspects, the lead frame comprises multiple die attach segments separated by slots, where at least one of the multiple die attach segments supports the die along its horizontal axis. At least one of the slots mitigates a current loop arising from operation of at least one of the magnetic field sensing elements.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 2, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Weidong Wang, Huang Huang, Natasha Healey
  • Publication number: 20250273546
    Abstract: A current sensor integrated circuit (IC) package includes an insulation structure disposed between a semiconductor die and a lead frame to control gap height and prevent the die from tilting and dropping the magnetic field coupling between the die the primary conductor. An insulation structure is disposed between the die and the lead frame such that the die remains level and magnetic coupling remains intact. An insulation structure may control the gap height between the lead frame and the die evenly during transfer molding, by supporting the die across its length and/or width. Epoxy dots are also or instead used to control the gap height and eliminate die tilt.
    Type: Application
    Filed: February 22, 2024
    Publication date: August 28, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: David Youm, Weidong Wang, Natasha Healey
  • Publication number: 20250201771
    Abstract: Systems, structures, packages, circuits, and methods provide IC packages with laminated substrates configured for use with or coupling to a transformer package or assembly. IC packages can include a substrate having an encapsulant presenting an encapsulating volume for encapsulation of one or more IC die. The encapsulating volume can be configured below, at, or above a main surface of the substrate, with the packages including receiving/mounting structures to accommodate coupling of a transformer assembly. The packages and modules may include various types of circuits; in some examples, chips, chip packages, or modules may include a gate driver or other high voltage circuit.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 19, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Harry Chandra, Natasha Healey
  • Publication number: 20250182950
    Abstract: A voltage-isolated transformer and integrated circuit package includes a substrate with opposed first and second surfaces and including a plurality of conductive traces, with a recess disposed in the second surface. The plurality of conductive traces includes a first group and a second group that are galvanically separate. A magnetic core is disposed on the first surface of the substrate. The magnetic core can include a soft ferromagnetic material. First and second coils are configured about the magnetic core and connected to the first and second groups of conductive traces, respectively, with the first and second coils and magnetic core being configured as a transformer. First and second integrated circuit die are disposed in the recess on the second surface. A dam is disposed on the first surface of the substrate and surrounding the magnetic core. An encapsulant disposed in the dam and encapsulating the magnetic core.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Harry Chandra, Natasha Healey
  • Publication number: 20250182948
    Abstract: Systems, structures, packages, circuits, and methods provide leadless transformer packages for galvanic isolation. An example leadless transformer includes a substrate including opposed first and second surfaces and a plurality of conductive traces. The plurality of conductive traces includes a first group and a second group that are galvanically separate. The first group includes a plurality of exposed portions that are exposed at a first area of the substrate and the second group includes a plurality of exposed portions that are exposed at a second area of the substrate. A magnetic core is disposed on the substrate. First and second coils are each disposed about the magnetic core and configured for connection to the first and second groups of conductive traces, respectively. The package includes a dam disposed on the substrate and configured to surround the magnetic core, and an encapsulant is within the dam, encapsulating the magnetic core.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Harry Chandra, Natasha Healey
  • Publication number: 20250174611
    Abstract: Systems, structures, packages, circuits, and methods provide leadframe-based packages with integrated IC-transformer structures having a transformer providing galvanic isolation for included IC die. An example leadframe-based voltage-isolated IC package includes a leadframe substrate with first and second leadframe, a magnetic core disposed on one side of the leadframe substrate, first and second IC die disposed on the other side of the leadframe substrate, a body including molding material encapsulating the first and second IC die; first and second coils configured about the magnetic core, and a wall configured to surround the magnetic core. The packages and modules may include various types of circuits; in some examples, chip packages or modules may include a galvanically isolated gate driver or other high voltage circuit.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Harry Chandra, Natasha Healey, Harianto Wong
  • Publication number: 20250140673
    Abstract: According to one aspect of the present disclosure, a voltage isolated integrated circuit (IC) package configuration includes a first package comprising a transformer and a mold material enclosing the transformer to form a first package body, wherein the first package comprises a first lead set to permit electrical connection to the transformer. In some embodiments, a second package comprising a lead frame, two or more semiconductor die supported by the lead frame, and a mold material enclosing the two or more semiconductor die to form a second package body, wherein the lead frame comprises a second lead set to permit electrical connection to the two or more semiconductor die. In some embodiments, the one or more leads of the first lead set is directly electrically connected to one or more leads of the second lead set, wherein the first package and the second package are mechanically coupled together.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Vijay Mangtani, Paul A. David, William P. Taylor, Harianto Wong, Natasha Healey, Harry Chandra
  • Patent number: 12163983
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: December 10, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Robert A. Briano, Natasha Healey
  • Patent number: 11800813
    Abstract: Methods and apparatus for providing a high isolation current sensor. In embodiments, a current sensor includes a leadframe having a current conductor first portion and a second portion, a magnetic field sensing element positioned in relation to the current conductor for detecting a magnetic generated by current flow through the current conductor, and a die supported by at least a portion of the first and/or second portions of the leadframe, wherein the first portion of the lead frame includes an isolation region aligned with a first edge of the die. In embodiments, a current sensor includes SOI processing and features to enhance active layer isolation.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 24, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Alexander Latham, Natasha Healey
  • Patent number: 11644485
    Abstract: A current sensor integrated circuit configured to sense a current through a current conductor includes a lead frame at least one signal lead, a fan out wafer level package (FOWLP), and a mold material enclosing the FOWLP and a portion of the lead frame. The FOWLP includes a semiconductor die configured to support at least one magnetic field sensing element to sense a magnetic field associated with the current, wherein the semiconductor die has a first surface on which at least one connection pad is accessible, a redistribution layer in contact with the at least one connection pad, and an insulating layer in contact with the redistribution layer, wherein the insulating layer is configured to extend beyond a periphery of the semiconductor die by a minimum distance. The die connection pad is configured to be electrically coupled to the at least one signal lead.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 9, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Natasha Healey
  • Publication number: 20230110671
    Abstract: A current sensor integrated circuit configured to sense a current through a current conductor includes a lead frame at least one signal lead, a fan out wafer level package (FOWLP), and a mold material enclosing the FOWLP and a portion of the lead frame. The FOWLP includes a semiconductor die configured to support at least one magnetic field sensing element to sense a magnetic field associated with the current, wherein the semiconductor die has a first surface on which at least one connection pad is accessible, a redistribution layer in contact with the at least one connection pad, and an insulating layer in contact with the redistribution layer, wherein the insulating layer is configured to extend beyond a periphery of the semiconductor die by a minimum distance. The die connection pad is configured to be electrically coupled to the at least one signal lead.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 13, 2023
    Applicant: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Natasha Healey
  • Publication number: 20230060219
    Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 2, 2023
    Applicant: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Robert A. Briano, Natasha Healey
  • Patent number: 11519939
    Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 6, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Shaun D. Milano, Rishikesh Nikam, Alexander Latham, Wade Bussing, Natasha Healey, Georges El Bacha
  • Publication number: 20210405092
    Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Shaun D. Milano, Rishikesh Nikam, Alexander Latham, Wade Bussing, Natasha Healey, Georges El Bacha
  • Publication number: 20210376227
    Abstract: Methods and apparatus for providing a high isolation current sensor. In embodiments, a current sensor includes a leadframe having a current conductor first portion and a second portion, a magnetic field sensing element positioned in relation to the current conductor for detecting a magnetic generated by current flow through the current conductor, and a die supported by at least a portion of the first and/or second portions of the leadframe, wherein the first portion of the lead frame includes an isolation region aligned with a first edge of the die. In embodiments, a current sensor includes SOI processing and features to enhance active layer isolation.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Alexander Latham, Natasha Healey
  • Patent number: 11183436
    Abstract: A power integrated circuit (IC) includes a lead frame comprising a signal lead, a power lead, and a paddle attached to one or more of the signal lead and the power lead, an electrical component supported by the paddle, and a mold material configured to enclose a portion of the lead frame and expose a surface of the paddle, wherein the power lead has a first portion extending from an edge of the mold material outside of the mold material in a first direction and a second portion enclosed by the mold material and extending from the edge of the mold material inside the mold material in a second direction to the paddle, wherein the second direction is substantially opposite to the first direction. In embodiments, the paddle is only attached to the second portion of the power lead.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 23, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Natasha Healey, Rishikesh Nikam
  • Patent number: 11150273
    Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 19, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Shaun D. Milano, Rishikesh Nikam, Alexander Latham, Wade Bussing, Natasha Healey, Georges El Bacha