Patents by Inventor Nathalie Cossement

Nathalie Cossement has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Task concurrency management design method
    Patent number: 7831951
    Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: November 9, 2010
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, University of Patras
    Inventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins
  • TASK CONCURRENCY MANAGEMENT DESIGN METHOD
    Publication number: 20070245273
    Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
    Type: Application
    Filed: June 11, 2007
    Publication date: October 18, 2007
    Applicant: Interuniversitair Microelektronica Centrum
    Inventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins
  • Task concurrency management design method
    Patent number: 7234126
    Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: June 19, 2007
    Assignees: Interuniversitair Microelektronica Centrum, Katholieke Universiteit Leuven, Patras, University of
    Inventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins
  • Task concurrency management design method
    Publication number: 20020099756
    Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of said digital system, wherein the system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
    Type: Application
    Filed: August 22, 2001
    Publication date: July 25, 2002
    Inventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins