Patents by Inventor Nathan A. Aldrich

Nathan A. Aldrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7322014
    Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: January 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Nathan A. Aldrich, Ruiqi Tian
  • Publication number: 20070061768
    Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
    Type: Application
    Filed: November 1, 2006
    Publication date: March 15, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Edward Travis, Nathan Aldrich, Ruiqi Tian
  • Patent number: 7146593
    Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: December 5, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Nathan A. Aldrich, Ruiqi Tian
  • Publication number: 20050097490
    Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 5, 2005
    Inventors: Edward Travis, Nathan Aldrich, Ruiqi Tian