Patents by Inventor Nathan A. Eckel
Nathan A. Eckel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250045388Abstract: Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.Type: ApplicationFiled: July 3, 2024Publication date: February 6, 2025Inventors: Nathan A. Eckel, Chun-Yi Liu, Lance P. Johnson, James Brian Johnson, Yang Lu
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Publication number: 20250045389Abstract: Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.Type: ApplicationFiled: July 3, 2024Publication date: February 6, 2025Inventors: Chun-Yi Liu, Lance P. Johnson, Nathan A. Eckel, James Brian Johnson
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Publication number: 20250023727Abstract: An apparatus comprises an encryption key generator to generate a media encryption key to encrypt data in number of memory components, where the encryption key generator is configured to wrap the media encryption key to generate an encrypted media encryption key, The encrypted media encryption key is stored in a non-volatile memory. The apparatus comprises firmware having instructions to transition the apparatus to and from a secure state using the encrypted media encryption key.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Inventors: Nathan A. Eckel, Steven D. Check
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Publication number: 20240402925Abstract: Methods, systems, and devices for boot and initialization techniques for stacked memory architectures are described. A memory system may include a common logic block operable to output an indication to each of a set of multiple interface blocks to initiate an initialization program, an evaluation program, or both, where the interface blocks may each be operable to access memory arrays via a respective set of one or more channels. The common logic block may receive a command to initialize or evaluate operations associated with the interface blocks or the respective memory arrays. The common logic block may output an indication of a set of instructions associated with the initialization or evaluation. The interface blocks may, using the received indication, obtain the instructions and perform one or more operations associated with the instructions. In some examples, the common logic block may output the indication in response to identifying a power-on condition.Type: ApplicationFiled: May 22, 2024Publication date: December 5, 2024Inventor: Nathan A. Eckel
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Publication number: 20240402909Abstract: Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.Type: ApplicationFiled: May 21, 2024Publication date: December 5, 2024Inventors: Nathan A. Eckel, Lance P. Johnson, Paul A. Laberge
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Publication number: 20240403165Abstract: Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry.Type: ApplicationFiled: May 17, 2024Publication date: December 5, 2024Inventors: Nathan A. Eckel, James Brian Johnson, Paul A. Laberge
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Publication number: 20240404581Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.Type: ApplicationFiled: May 17, 2024Publication date: December 5, 2024Inventors: Ameen D. Akel, Brent Keeth, James Brian Johnson, Chun-Yi Liu, Shivasankar Gunasekaran, Paul A. Laberge, Gregory A. King, Sai Krishna Mylavarapu, Su Wei Lim, Nathan A. Eckel, Lance P. Johnson, Nathan D. Henningson
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Patent number: 12137162Abstract: An apparatus comprises an encryption key generator to generate a media encryption key to encrypt data in number of memory components, where the encryption key generator is configured to wrap the media encryption key to generate an encrypted media encryption key, The encrypted media encryption key is stored in a non-volatile memory. The apparatus comprises firmware having instructions to transition the apparatus to and from a secure state using the encrypted media encryption key.Type: GrantFiled: June 28, 2021Date of Patent: November 5, 2024Inventors: Nathan A. Eckel, Steven D. Check
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Patent number: 11650925Abstract: A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.Type: GrantFiled: December 17, 2019Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Eric R. Fox, Nathan A. Eckel
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Patent number: 11579979Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.Type: GrantFiled: July 22, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: James E. Dunn, Nathan A. Eckel
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Patent number: 11579791Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: October 7, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Jeffery J. Leyda, Nathan A. Eckel
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Patent number: 11514995Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.Type: GrantFiled: March 24, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Nathan A. Eckel, Keith A. Benjamin
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Publication number: 20210349783Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Inventors: James E. Dunn, Nathan A. Eckel
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Publication number: 20210328790Abstract: An apparatus comprises an encryption key generator to generate a media encryption key to encrypt data in number of memory components, where the encryption key generator is configured to wrap the media encryption key to generate an encrypted media encryption key, The encrypted media encryption key is stored in a non-volatile memory. The apparatus comprises firmware having instructions to transition the apparatus to and from a secure state using the encrypted media encryption key.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Nathan A. Eckel, Steven D. Check
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Patent number: 11074131Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.Type: GrantFiled: April 13, 2020Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: James E. Dunn, Nathan A. Eckel
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Patent number: 11070375Abstract: An apparatus comprises an encryption key generator to generate a media encryption key to encrypt data in number of memory components, where the encryption key generator is configured to wrap the media encryption key to generate an encrypted media encryption key, The encrypted media encryption key is stored in a non-volatile memory. The apparatus comprises firmware having instructions to transition the apparatus to and from a secure state using the encrypted media encryption key.Type: GrantFiled: August 14, 2018Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Nathan A. Eckel, Steven D. Check
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Publication number: 20210210155Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Inventors: Nathan A. Eckel, Keith A. Benjamin
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Publication number: 20210182201Abstract: A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Eric R. Fox, Nathan A. Eckel
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Patent number: 10984881Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.Type: GrantFiled: December 13, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Nathan A. Eckel, Keith A. Benjamin
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Publication number: 20210019073Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: October 7, 2020Publication date: January 21, 2021Inventors: Jeffery J. Leyda, Nathan A. Eckel