Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Abstract: In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.