Patents by Inventor Nathan Bertrand

Nathan Bertrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Footwear for inversion exercises
    Patent number: 12207704
    Abstract: An inversion footwear to enable a human to hang in an inverted position from an elevated bar or other elevated device. The inversion footwear can include either a padding at a front upper portion of the inversion footwear, a hook-like extension at a back of the inversion footwear, or a hook at a bottom of the inversion footwear can be used to grip the elevated bar or other elevated device to secure the human wearing the inversion footwear thereto while hanging in an inverted position.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 28, 2025
    Inventor: Nathan Bertrand
  • FOOTWEAR FOR INVERSION EXERCISES
    Publication number: 20240108095
    Abstract: An inversion footwear to enable a human to hang in an inverted position from an elevated bar or other elevated device. The inversion footwear can include either a padding at a front upper portion of the inversion footwear, a hook-like extension at a back of the inversion footwear, or a hook at a bottom of the inversion footwear can be used to grip the elevated bar or other elevated device to secure the human wearing the inversion footwear thereto while hanging in an inverted position.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Inventor: Nathan Bertrand
  • System and method for evaluating power and ground vias in a package design
    Patent number: 7272806
    Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: September 18, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy Nelson, Nathan Bertrand
  • System and method for evaluating vias per pad in a package design
    Patent number: 6907589
    Abstract: A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: June 14, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy Nelson, Nathan Bertrand
  • System and method for evaluating vias per pad in a package design
    Publication number: 20040163054
    Abstract: A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 19, 2004
    Inventors: Mark D. Frank, Jerimy Nelson, Nathan Bertrand
  • System and method for evaluating power and ground vias in a package design
    Publication number: 20040162715
    Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 19, 2004
    Inventors: Mark D. Frank, Jerimy Nelson, Nathan Bertrand