Patents by Inventor Nathan Buck
Nathan Buck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8769452Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: GrantFiled: October 31, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20140173543Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: ApplicationFiled: December 23, 2013Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123089Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123095Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: December 23, 2013Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140123086Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8560989Abstract: Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.Type: GrantFiled: December 6, 2011Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Jeffrey G. Hemmett, Debjit Sinha, Natesan Venkateswaran, Chandramouli Visweswariah, Michael H. Wood, Vladimir Zolotov
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Publication number: 20130145333Abstract: Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, James C. GREGERSON, Peter A. HABITZ, Jeffrey G. HEMMETT, Debjit SINHA, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Michael H. WOOD, Vladimir ZOLOTOV
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Patent number: 8086988Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.Type: GrantFiled: May 18, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Nathan Buck, Howard H. Chen, James P. Eckhardt, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Susan K. Lichtensteiger, Chandramouli Visweswariah, Tad J. Wilder
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Publication number: 20100293512Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.Type: ApplicationFiled: May 18, 2009Publication date: November 18, 2010Applicant: International Business Machines CorporationInventors: Nathan Buck, Howard H. Chen, James P. Eckhardt, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Susan K. Lichtensteiger, Chandramouli Visweswariah, Tad J. Wilder