Abstract: Methods and systems for performing a Mapping of Address and Port using translation (MAP-T) data plane verification. A method for performing a MAP-T data plane verification includes initiating, by a diagnostic server provisioned with at least MAP-T diagnostic rules, a MAP-T diagnostic on a border relay provisioned with MAP-T rules, generating, by the diagnostic server, a diagnostic packet per the MAP-T diagnostic rules, sending, by the diagnostic server, the diagnostic packet to the border relay, performing, by the border relay, a translation on the diagnostic packet per the provisioned MAP-T rules, analyzing, by the diagnostic server to generate a report, at least a translation accuracy of a received translated diagnostic packet, and configuring at least one device based on a received report.

Abstract: Methods and systems for performing a Mapping of Address and Port using translation (MAP-T) data plane verification. A method for performing a MAP-T data plane verification includes initiating, by a diagnostic server provisioned with at least MAP-T diagnostic rules, a MAP-T diagnostic on a border relay provisioned with MAP-T rules, generating, by the diagnostic server, a diagnostic packet per the MAP-T diagnostic rules, sending, by the diagnostic server, the diagnostic packet to the border relay, performing, by the border relay, a translation on the diagnostic packet per the provisioned MAP-T rules, analyzing, by the diagnostic server to generate a report, at least a translation accuracy of a received translated diagnostic packet, and configuring at least one device based on a received report.

Abstract: Methods and systems for an accelerated and offload dual border relay. A method includes receiving, by a hardware border relay from a network device, an Internet Protocol (IP) packet, determining, by the hardware border relay, a packet type of the IP packet, translating, by the hardware border relay provisioned with IPv6 transition technology rules, the IP packet to a hardware translated IP packet when the IP packet is a first type, translating, by the offload border relay provisioned with MAP-T rules, the IP packet to an offload translated IP packet when the IP packet is a second type, transmitting, by the offload border relay to the hardware border relay, the offload translated IP packet when the IP packet is the second type, and transmitting, by the hardware border relay, one of the offload translated IP packet and the hardware translated IP packet to another network device.

Abstract: Methods and systems for performing a Mapping of Address and Port using translation (MAP-T) data plane verification. A method for performing a MAP-T data plane verification includes initiating, by a diagnostic server provisioned with at least MAP-T diagnostic rules, a MAP-T diagnostic on a border relay provisioned with MAP-T rules, generating, by the diagnostic server, a diagnostic packet per the MAP-T diagnostic rules, sending, by the diagnostic server, the diagnostic packet to the border relay, performing, by the border relay, a translation on the diagnostic packet per the provisioned MAP-T rules, analyzing, by the diagnostic server to generate a report, at least a translation accuracy of a received translated diagnostic packet, and configuring at least one device based on a received report.

Abstract: Methods and systems for performing a Mapping of Address and Port using translation (MAP-T) data plane verification. A method for performing a MAP-T data plane verification includes initiating, by a diagnostic server provisioned with at least MAP-T diagnostic rules, a MAP-T diagnostic on a border relay provisioned with MAP-T rules, generating, by the diagnostic server, a diagnostic packet per the MAP-T diagnostic rules, sending, by the diagnostic server, the diagnostic packet to the border relay, performing, by the border relay, a translation on the diagnostic packet per the provisioned MAP-T rules, analyzing, by the diagnostic server to generate a report, at least a translation accuracy of a received translated diagnostic packet, and configuring at least one device based on a received report.

Abstract: Methods and systems for an accelerated and offload dual border relay. A method includes receiving, by a hardware border relay from a network device, an Internet Protocol (IP) packet, determining, by the hardware border relay, a packet type of the IP packet, translating, by the hardware border relay provisioned with IPv6 transition technology rules, the IP packet to a hardware translated IP packet when the IP packet is a first type, translating, by the offload border relay provisioned with MAP-T rules, the IP packet to an offload translated IP packet when the IP packet is a second type, transmitting, by the offload border relay to the hardware border relay, the offload translated IP packet when the IP packet is the second type, and transmitting, by the hardware border relay, one of the offload translated IP packet and the hardware translated IP packet to another network device.

Abstract: The invention is directed to an amplifier including an absolute value circuit. The absolute value circuit may be driven by differential potentials and may include a first pair of transistors modulating a tail current of the amplifier when a differential input voltage goes high, and a second pair of transistors modulating the tail current of the amplifier when a differential input voltage goes low.

Abstract: The invention is directed to an amplifier including an absolute value circuit. The absolute value circuit may be driven by differential potentials and may include a first pair of transistors modulating a tail current of the amplifier when a differential input voltage goes high, and a second pair of transistors modulating the tail current of the amplifier when a differential input voltage goes low.

Abstract: A system and method are presented for qualifying a component. The system includes a receiving station, a control section, a plurality of test/inspection stations, a data storage section and a marking station. The receiving station receives a component. The control section includes a processor. The plurality of test/inspection stations each include equipment to measure one or more of physical, compositional and resistance properties of the component. The processor and the equipment cooperate to compare the measured properties to predefined properties for acceptance of the component, and to determine conformance between the measured properties and the predefined properties to qualify the component for use. The data storage section includes data store that receives and stores the predefined properties, the unique identifier, and the measured properties of the component. The marking station includes marking equipment to mark the component with the unique identifier.

Abstract: A bipolar rail-to-rail input stage includes complementary differential input pairs, and a switching circuit which makes one or the other of the input pairs active depending on the relationship between a transition threshold voltage Vth and the common mode input voltage Vcm. A transition threshold voltage selection circuit provides a selectable one of at least two different Vth voltages to the switching circuit in response to a select signal. In one embodiment, the select signal has logic “high”, logic “low”, and “floating” states. The transition threshold voltage selection circuit provides a first Vth voltage when the select signal is in a first state, a second Vth voltage when the select signal is in a second state, and disables the input stage when the select signal is in a third state.

Abstract: A bipolar rail-to-rail input stage with emitter degeneration includes a current reduction circuit arranged to reduce the amount of current which the PNP and NPN input pairs would otherwise conduct when the common mode input voltage is such that both pairs are conducting. The current reduction circuit is preferably arranged such that the transconductance (Gm2) of the input stage when both pairs are conducting is equal to its transconductance (Gm) when only one pair is active. The current reduction circuit preferably comprises a current shunt circuit made from four bipolar transistors: a pair of PNP transistors, the emitters of which are connected to respective emitters of the PNP input transistors, and a pair of NPN transistors, the emitters of which are connected to respective emitters of the NPN input transistors, with the bases and collectors of all four shunt transistors connected together at a summing node.