Patents by Inventor Nathan Charland

Nathan Charland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9202073
    Abstract: This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 1, 2015
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Bert Marston, John R. Turner, Michael Smith, Kenneth P. Snowdon, Nathan Charland
  • Patent number: 8829932
    Abstract: This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John R. Turner, Nathan Charland
  • Publication number: 20140219442
    Abstract: This document discusses, among other things, a method of distributing authentication keys that can prevent certain forms of circuit fabrication piracy. In an example, a method can include selecting a number of authentication keys for generation at a key generation computer, generating a random number using a random number generator of the key generation computer, generating the number of authentication keys using the random number and a key generation algorithm stored in the memory of the key generation computer, scrambling each of the number of authentication keys using a scrambling routine executing on the key generation computer, and distributing the scrambled authentication keys to an authorized manufacturers.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 7, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Robert A. Card, Jefferson Hopkins, Christian Klein, Myron J. Miske, Michael Smith, John R. Turner, Jaeyoung Yoo, Nathan Charland
  • Publication number: 20140143887
    Abstract: This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 22, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Bert Marston, John R. Turner, Michael Smith, Kenneth P. Snowdon, Nathan Charland
  • Publication number: 20120019273
    Abstract: This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 26, 2012
    Inventors: John R. Turner, Nathan Charland
  • Publication number: 20050207280
    Abstract: A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. Two data boundary bits are inserted between the word data bits, the boundary data bits are arranged with a logic level transition between the two data boundary bits. Also, at the boundary of the words during the sending of the two boundary data bits, the synchronous bit clock is arranged to have no logic level transition. The receiving system will use the bit clock to serial load the received word and boundary data bits into a shift register.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 22, 2005
    Inventors: Michael Fowler, James Boomer, Nathan Charland