Patents by Inventor Nathan D. Dias

Nathan D. Dias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Technique to assess timing delay by use of layout quality analyzer comparison
    Patent number: 6877147
    Abstract: In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: April 5, 2005
    Assignee: Broadcom Corporation
    Inventors: David A. Kidd, Nathan D. Dias, Matthew J. Page
  • Layout quality analyzer
    Publication number: 20040015805
    Abstract: In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Inventors: David A. Kidd, Nathan D. Dias, Matthew J. Page