Patents by Inventor Nathan Dohm
Nathan Dohm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8531968Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.Type: GrantFiled: August 31, 2010Date of Patent: September 10, 2013Assignee: Jinsalas Solutions, LLCInventors: David Mayhew, Karl Meier, Nathan Dohm
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Patent number: 7953024Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.Type: GrantFiled: April 13, 2009Date of Patent: May 31, 2011Assignee: Jinsalas Solutions, LLCInventors: David Mayhew, Nathan Dohm
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Patent number: 7916743Abstract: The present invention provides an improved architecture and method for the processing and transmission of multicast packets within a switching device. Briefly, as multicast packets arrive, a copy of the packet, or preferably a pointer for it, is placed in a multicast FIFO. As each pointer reaches the head of the FIFO, the destination output ports via which the packet is to be transmitted are determined, based on the packet's multicast group identifier (MGID). In the preferred embodiment, there is a dedicated multicast output queue associated with each output port. Copies of the packet, or preferably pointers to the packet, are then stored in those output queues associated with the specified destination output ports. In this way, a congested output port only affects the transmission of multicast packets via that congested port.Type: GrantFiled: November 17, 2004Date of Patent: March 29, 2011Assignee: Jinsalas Solutions, LLCInventor: Nathan Dohm
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Publication number: 20110044175Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.Type: ApplicationFiled: August 31, 2010Publication date: February 24, 2011Inventors: David Mayhew, Karl Meier, Nathan Dohm
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Patent number: 7809007Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.Type: GrantFiled: March 5, 2004Date of Patent: October 5, 2010Inventors: David Mayhew, Karl Meier, Nathan Dohm
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Publication number: 20100097933Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.Type: ApplicationFiled: April 13, 2009Publication date: April 22, 2010Inventors: David Mayhew, Nathan Dohm
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Patent number: 7518996Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.Type: GrantFiled: September 16, 2004Date of Patent: April 14, 2009Assignee: Jinsalas Solutions, LLCInventors: David Mayhew, Nathan Dohm
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Patent number: 7451282Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.Type: GrantFiled: March 9, 2005Date of Patent: November 11, 2008Assignee: Dolphin Interconnect Solutions North America Inc.Inventors: Karl Meier, Nathan Dohm
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Publication number: 20060203570Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.Type: ApplicationFiled: March 9, 2005Publication date: September 14, 2006Inventors: Karl Meier, Nathan Dohm
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Publication number: 20060106967Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.Type: ApplicationFiled: November 12, 2005Publication date: May 18, 2006Inventors: Lynne Brocco, Todd Comins, Nathan Dohm, David Mayhew, Carey McMaster
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Publication number: 20060104275Abstract: The present invention provides an improved architecture and method for the processing and transmission of multicast packets within a switching device. Briefly, as multicast packets arrive, a copy of the packet, or preferably a pointer for it, is placed in a multicast FIFO. As each pointer reaches the head of the FIFO, the destination output ports via which the packet is to be transmitted are determined, based on the packet's multicast group identifier (MGID). In the preferred embodiment, there is a dedicated multicast output queue associated with each output port. Copies of the packet, or preferably pointers to the packet, are then stored in those output queues associated with the specified destination output ports. In this way, a congested output port only affects the transmission of multicast packets via that congested port.Type: ApplicationFiled: November 17, 2004Publication date: May 18, 2006Inventor: Nathan Dohm
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Publication number: 20060056292Abstract: The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.Type: ApplicationFiled: September 16, 2004Publication date: March 16, 2006Inventors: David Mayhew, Nathan Dohm
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Publication number: 20050195845Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.Type: ApplicationFiled: March 5, 2004Publication date: September 8, 2005Inventors: David Mayhew, Karl Meier, Nathan Dohm
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Publication number: 20050080959Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.Type: ApplicationFiled: September 21, 2004Publication date: April 14, 2005Inventors: Lynne Brocco, Todd Comins, Nathan Dohm, David Mayhew, Carey McMaster
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Publication number: 20050080976Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.Type: ApplicationFiled: September 21, 2004Publication date: April 14, 2005Inventors: Lynne Brocco, Todd Comins, Nathan Dohm, David Mayhew, Carey McMaster
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Patent number: RE44402Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.Type: GrantFiled: November 10, 2010Date of Patent: July 30, 2013Assignee: Jinsalas Solutions, LLCInventors: Karl Meier, Nathan Dohm