Abstract: Clock generation circuitry is arranged in stages so as to convert a slow slew rate input signal into a high slew rate clock signal in a low power environment. Each stage includes a capacitor and an inverter, both fed by respective current mirrors. The capacitor is trickle-charged through its current mirror, and charge of the capacitor is dumped onto an output of the stage at a controlled timing. Two or more such stages may be provided, so as to improve the slew rate of both of the leading and trailing edges of the clock signal, and also so as to provide a convenient source of timing for dumping charge of each capacitor. Each stage might also include a diode switchably connected across the capacitor, so as to discharge the capacitor at appropriate timings, to reduce interference on succeeding stages that might otherwise be caused by residual charge on the capacitor.