Patents by Inventor Nathan Francis Sheeley
Nathan Francis Sheeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409233Abstract: Buffer assignment in a contiguous area in a coarse-grained reconfigurable (CGR) array is optimized by temporarily assigning a first buffer portion and a second buffer portion to first and second physical memory units, routing connections in the contiguous area, and calculating a first cost. A list of candidates for a third physical memory unit is created, and a best cost and a best candidate are initialized. For each candidate, the first and second buffer are reassigned to the candidate, connections for data and dataflow control information in the contiguous area are routed, and a second cost is calculated. If the second cost is better than the best cost, the best cost and the best candidate are updated.Type: ApplicationFiled: November 15, 2022Publication date: December 21, 2023Applicant: SambaNova Systems, Inc.Inventors: Nathan Francis SHEELEY, Raghu PRABHAKAR, David Alan KOEPLINGER
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Patent number: 11561925Abstract: A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.Type: GrantFiled: September 16, 2021Date of Patent: January 24, 2023Assignee: SambaNova Systems, Inc.Inventors: Raghu Prabhakar, Nathan Francis Sheeley, Matheen Musaddiq, Scott Layson Burson, Sitanshu Gupta, Sumti Jairath, Pramod Nataraja, Ajit Punj
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Publication number: 20220309029Abstract: A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.Type: ApplicationFiled: September 16, 2021Publication date: September 29, 2022Applicant: SambaNova Systems, Inc.Inventors: Raghu PRABHAKAR, Nathan Francis SHEELEY, Matheen MUSADDIQ, Scott Layson BURSON, Sitanshu GUPTA, Sumti JAIRATH, Pramod NATARAJA, Ajit PUNJ
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Patent number: 11443014Abstract: The technology disclosed relates to matrix multiplication where the multiplier can be a sparse matrix. In particular, a multiplication device includes first circuitry configured to obtain the multiplicand matrix and an index of columns of the multiplier matrix and to generate an intermediate matrix that has one row per entry in the index copied from a respective row of the multiplicand matrix based on a value of a corresponding entry in the index. The device also includes second circuitry configured to receive the intermediate matrix from the first circuitry, obtain non-zero values of the multiplier matrix and a list of a number of non-zero entries per row of the multiplier matrix, and generate a product matrix as a result of multiplies of the non-zero values of the multiplier matrix and the intermediate matrix.Type: GrantFiled: November 5, 2021Date of Patent: September 13, 2022Assignee: SambaNova Systems, Inc.Inventors: Mingran Wang, Raghu Prabhakar, Darshan Dhimantkumar Gandhi, Maulik Subhash Desai, Nathan Francis Sheeley, Scott Layson Burson, Sitanshu Gupta
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Patent number: 11366783Abstract: An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.Type: GrantFiled: March 29, 2021Date of Patent: June 21, 2022Assignee: SambaNova Systems, Inc.Inventors: Raghu Prabhakar, Nathan Francis Sheeley, Amitabh Menon, Sitanshu Gupta, Sumti Jairath, Matheen Musaddiq
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Patent number: 11204889Abstract: A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.Type: GrantFiled: March 29, 2021Date of Patent: December 21, 2021Assignee: SambaNova Systems, Inc.Inventors: Raghu Prabhakar, Nathan Francis Sheeley, Matheen Musaddiq, Scott Layson Burson, Sitanshu Gupta, Sumti Jairath, Pramod Nataraja, Ajit Punj
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Patent number: 8448107Abstract: This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.Type: GrantFiled: July 8, 2009Date of Patent: May 21, 2013Assignee: Apple Inc.Inventors: Nathan Francis Sheeley, Mark H. Nodine, Nicolas Xavier Pena, Irfan Waheed, Patrick Peters, Adrian J. Isles
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Publication number: 20110214096Abstract: This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.Type: ApplicationFiled: July 8, 2009Publication date: September 1, 2011Applicant: INTRINSITY, INC.Inventors: Nathan Francis Sheeley, Mark H. Nodine, Nicolas Xavier Pena, Irfan Waheed, Patrick Peters, Adrian J. Isles