Patents by Inventor Nathan Geryk

Nathan Geryk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6446873
    Abstract: Briefly, in accordance with one embodiment of the invention, a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: September 10, 2002
    Assignee: Intel Corporation
    Inventor: Nathan Geryk
  • Patent number: 6166441
    Abstract: Briefly, in accordance with one embodiment of the invention a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides.Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: December 26, 2000
    Assignee: Intel Corporation
    Inventor: Nathan Geryk