Abstract: A bidirectional electroosmotic pump may be provided. The bidirectional electroosmotic pump may be made of materials that are biocompatible and non-ferrous. The bidirectional electroosmotic pump may be part of an implantable medical device for the purpose of medicine delivery. The bidirectional electroosmotic pump may contain a working fluid and may facilitate the delivery of a separate payload fluid. In an exemplary embodiment, the bidirectional pump may contain bellows which may allow the pump to deliver the payload fluid through a series of valves and/or catheters. In another embodiment the bidirectional electroosmotic pump may contain a pump sensing mechanism to monitor the state of the pump.

Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

Abstract: An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Abstract: A method of controlling write parameter selection in a memory device, can include: (i) storing a configuration set number in a configuration register, where the configuration register is accessible by a user via an interface; (ii) receiving a write command from a host via the interface; (iii) comparing the stored configuration set number against set numbers in a register block to determine a match or a mismatch; (iv) downloading configuration bits from a memory array into the register block in response to the mismatch determination; (v) selecting a configuration set corresponding to the stored configuration set number from the register block in response to the match determination; and (vi) using the selected configuration set to perform a write operation on the memory device to execute the write command.

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Abstract: A circuit can include a signal section that includes a first signal transistor configured to operate in a subthreshold region to maintain the signal node at about VCC as VCC rises from a low level; a high threshold section that enables a current path from the signal node to the low power supply node only after a voltage at the detect node exceeds a level greater than a threshold voltage (Vt); and an output section having transistors with relatively long channels, for reduced crowbar current.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.