Patents by Inventor Nathan Hu

Nathan Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10079916
    Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 18, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Kevin Y. Cheng, Nathan Hu
  • Publication number: 20170048358
    Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.
    Type: Application
    Filed: April 26, 2016
    Publication date: February 16, 2017
    Inventors: David A. Roberts, Kevin Y. Cheng, Nathan Hu
  • Publication number: 20090172675
    Abstract: Systems for context switching a requestor engine during an atomic process without corrupting the atomic process. Typically an atomic process cannot be interrupted prior to completion and if it is interrupted, the process will terminated abnormally resulting in a corrupted transaction. Systems that allow for a controlled interruption of an atomic process without corruption with subsequent context switching are presented. The system consists of a context-switchable requester engine, a context switch controller, shared resource synchronizer, and a shared resource system. The system may also containing multiple local and remote context-switchable requestor engines as well as multiple local and remote shared resource systems. A method for context switching a requestor engine during an atomic process without corrupting the atomic process is also presented.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Mark GROSSMAN, Nathan Hu