Patents by Inventor Nathan J. Shashoua

Nathan J. Shashoua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for generation of independent clock signals from the same oscillator
    Patent number: 11245406
    Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 8, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Harihara Subramanian Ranganathan, Xue-Mei Gong, James D. Barnette, Nathan J. Shashoua, Srisai Rao Seethamraju
  • METHOD FOR GENERATION OF INDEPENDENT CLOCK SIGNALS FROM THE SAME OSCILLATOR
    Publication number: 20210409031
    Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Harihara Subramanian Ranganathan, Xue-Mei Gong, James D. Barnette, Nathan J. Shashoua, Srisai Rao Seethamraju