Abstract: A method of authenticating a second electronic device at a first electronic device, the method comprising: providing at the second electronic device a memory, the memory comprising a first memory portion which has restricted access and is readable only when a first secret key is presented to the second electronic device; sending the first secret key from the first electronic device to the second electronic device; in response, sending a second secret key stored in the first memory portion from the second electronic device to the first electronic device; and authenticating the second secret key at the first electronic device.

Abstract: A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

Abstract: A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

Abstract: A memory device with a switchable clock output. The memory device has a data pin, a clock input pin, and a clock output pin. The memory device is designed to be wired up to a plurality of other memory devices in a daisy chain manner. The clock input pin of the first memory device would be serially coupled to the first memory device. The clock output pin of each memory device would be serially coupled to the clock input pin of a directly successive memory device. The processor can then interrogate the first memory device for the identification information it contains. Once this information is obtained, the processor can issue a command to deactivate the first memory device from responding to bus commands, as well as to output the clock signal via the clock output pin to a directly successive memory device. The processor may then interrogate the next memory device.

Abstract: A method for allowing flexible multiple access to a serial bus by a plurality of circuit boards. Before a circuit board can be used on a common serial bus with other circuit boards, a unique software address must be assigned to each circuit board. The unique software address is assigned by having a bus master device issue Assign Address commands which utilizes a unique serial number which is stored on each circuit board. The Assign Address command queries each of the circuit boards coupled to the serial bus and assigns a unique software address to each circuit board that fully responds. The Assign Address command is repeated for each circuit board on the serial bus until all of the circuit boards on the serial bus have been assigned a unique software address.