Patents by Inventor Nathan Joseph Sirocka
Nathan Joseph Sirocka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230105208Abstract: A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to receive a request for one of the plurality of independent plane driver circuits to execute a high current event on a corresponding one of the plurality of planes in the memory device. The control logic is further to increment a counter tracking a number of high current events occurring in the memory device, and determine whether the number of high current events occurring in the memory device satisfies a threshold criterion. Responsive to determining that the number of high current events occurring in the memory device satisfies the threshold criterion, the control logic is to cause execution of the high current event to be delayed.Type: ApplicationFiled: August 11, 2022Publication date: April 6, 2023Inventor: Nathan Joseph Sirocka
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Patent number: 11605425Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative section are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.Type: GrantFiled: June 17, 2021Date of Patent: March 14, 2023Assignee: Micron Technology, Inc.Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
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Patent number: 11527286Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.Type: GrantFiled: July 14, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Nathan Joseph Sirocka, Hari Giduturi
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Patent number: 11183237Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.Type: GrantFiled: September 29, 2020Date of Patent: November 23, 2021Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Nathan Joseph Sirocka, Byung Sick Moon, Jeffrey Edward Koelling
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Publication number: 20210343340Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Mingdong Cui, Nathan Joseph Sirocka, Hari Giduturi
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Publication number: 20210312981Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
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Patent number: 11133056Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.Type: GrantFiled: September 29, 2020Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Nathan Joseph Sirocka, Mingdong Cui
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Patent number: 11087838Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.Type: GrantFiled: October 22, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Nathan Joseph Sirocka, Hari Giduturi
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Patent number: 11074970Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.Type: GrantFiled: October 30, 2019Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
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Publication number: 20210134363Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Inventors: Nathan Joseph Sirocka, Mingdong Cui, Jeffrey Edward Koelling
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Publication number: 20210134364Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.Type: ApplicationFiled: September 29, 2020Publication date: May 6, 2021Inventors: Mingdong Cui, Nathan Joseph Sirocka, Byung Sick Moon, Jeffrey Edward Koelling
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Publication number: 20210118501Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.Type: ApplicationFiled: October 22, 2019Publication date: April 22, 2021Inventors: Mingdong Cui, Nathan Joseph Sirocka, Hari Giduturi
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Publication number: 20210118492Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.Type: ApplicationFiled: September 29, 2020Publication date: April 22, 2021Inventors: Nathan Joseph Sirocka, Mingdong Cui
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Patent number: 10847222Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.Type: GrantFiled: October 30, 2019Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Nathan Joseph Sirocka, Byung Sick Moon, Jeffrey Edward Koelling
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Patent number: 10818345Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.Type: GrantFiled: October 22, 2019Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Nathan Joseph Sirocka, Mingdong Cui