Abstract: A pillow includes a first pillow cushion consisting essentially of a gelatinous elastomer that is sized and configured to support a head and neck of a person using the pillow cushion and a second pillow cushion coupled thereto. The pillow cushion has deformable wall members located and configured to define voids therebetween such that the deformable wall members may be displaced into adjacent voids upon deformation of the deformable wall members. The deformable wall members are configured to buckle when a pressure applied to a cushioning surface of the first pillow cushion, in a direction perpendicular to a first major surface, exceeds a threshold pressure level. A pillow cover covers the first pillow cushion and the second pillow cushion. A method of fabricating a pillow includes enclosing such first and second pillow cushions in a pillow cover.

Abstract: A method for facilitating the evaluation of candidates in an evaluation process is provided. The method includes operations of receiving a set of evaluation data from a candidate evaluation system, the set of evaluation data including at least evaluation ratings data and evaluation recommendation data for a set of candidate. The method further includes providing a user interface to a decision maker to display a performance of each of a set of candidates in a two-dimensional graphic representation. The method further includes receiving a first weighting for a first subset of the evaluation data and updating the graphic representation to show a weighted performance of each of the candidates in the evaluation. The updating is based on the first weighting received from the decision maker.

Abstract: A flash electrically erasable and programmable read only memory (EEPROM) having a selective parallel sector erase capability (100) is disclosed. The flash EEPROM (100) includes a number of sectors (104-0 to 104-18), each of which receives an erase voltage (VCC) by way of a source switch circuit (112-0 to 112-18). The source switch circuits (112-0 to 112-18) are each enabled by logic values stored in corresponding tag registers (114-0 to 114-18). The logic values stored by the tag registers (114-0 to 114-18) can be established by the application of particular address values (A12 to A18). The logic values of the tag registers (114-0 to 114-18) can be simultaneously reset to the same value by the application of other address values (A9).