Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.

Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.

Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.

Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.

Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

Abstract: Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

Abstract: An arrangement, a method and a system to read information stored in a layer of ferroelectric media.

Abstract: An arrangement, a method and a system to read information stored in a layer of ferroelectric media. The arrangement includes a layer including a ferroelectric media having one or more ferroelectric domains holding bit charges, a domain corresponding to information; a probe having a tip, wherein the media and the tip are adapted to move relative to one another such that the tip scans the ferroelectric domains of the media while applying a contact force to the domains to generate a direct piezoelectric effect within the domains; and circuitry coupled to the tip and adapted to generate a signal in response to an electrical coupling between the tip and the domains while scanning the tip in contact with the domains, the signal corresponding to a readout signal for ferroelectric bit charges stored in the media.

Abstract: Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

Abstract: An apparatus comprising a substrate, an electrode coupled to the substrate, a modifiable layer coupled to the electrode, and a current focusing layer coupled to the modifiable layer. The current focusing layer comprises a conductive region and an insulating region. A method comprising forming a modifiable layer on an electrode and forming a current focusing layer on the modifiable layer.

Abstract: In one embodiment, the present invention includes an apparatus having a conductive storage medium to store information in the form of electrostatic charge. The conductive storage medium can be disposed in a non-conductive layer that is formed over a charge blocking layer, which in turn may be disposed over an electrode layer. In one embodiment, a barrier layer may be disposed over the non-conductive layer. Other embodiments are described and claimed.

Abstract: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.

Abstract: An arrangement, a method and a system to read information stored in a layer of ferroelectric media.

Abstract: A memory media and a method to provide same. The memory media includes: a media layer comprising a ferroelectric layer having a bottom surface and a top surface; a plurality of adjacent charge domains defined in the ferroelectric layer, the domains including alternating up domains and down domains each extending between the bottom surface and the top surface; and a trapped charge region adjacent a top surface of the media layer, the trapped charge region including charges in addition to the charges present in the charge domains at regions thereof other than regions adjacent the top surface of the media layer.

Abstract: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.