Patents by Inventor Nathan Strutt

Nathan Strutt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11621395
    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Pedro Quintero, Oleg Golonzka
  • Patent number: 11502254
    Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Oleg Golonzka
  • Patent number: 11489112
    Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
  • Patent number: 11462684
    Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Albert Chen, Nathan Strutt, Oleg Golonzka, Pedro Quintero, Christopher J. Jezewski, Elijah V. Karpov
  • Patent number: 11430948
    Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 30, 2022
    Assignee: INTEL CORPORATION
    Inventors: Timothy Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka, Hiten Kothari, Matthew J. Andrus
  • Patent number: 11342499
    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Timothy E. Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka
  • Publication number: 20200343445
    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Applicant: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Pedro Quintero, Oleg Golonzka
  • Publication number: 20200203602
    Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
  • Publication number: 20200203603
    Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Timothy Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka, Hiten Kothari, Matthew J. Andrus
  • Publication number: 20200203605
    Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Albert CHEN, Nathan STRUTT, Oleg GOLONZKA, Pedro QUINTERO, Christopher J. JEZEWSKI, Elijah V. KARPOV
  • Publication number: 20200144496
    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
    Type: Application
    Filed: September 18, 2017
    Publication date: May 7, 2020
    Inventors: Timothy E. GLASSMAN, Dragos SEGHETE, Nathan STRUTT, Namrata S. ASURI, Oleg GOLONZKA
  • Publication number: 20200106013
    Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Oleg Golonzka
  • Patent number: 9815764
    Abstract: Homochiral metal organic framework (MOF) selected from a group consisting of (Sp)-P5A-MOF-1 and (Rp)-P5A-MOF-1 is provided. The homochiral MOFs are prepared from pure enantiomer struts of formula (I): The homochiral MOFs are suitable for separation of enantiomers from racemic mixtures.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 14, 2017
    Assignees: NORTHWESTERN UNIVERSITY, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY (KACST)
    Inventors: James Fraser Stoddart, Nathan Strutt
  • Publication number: 20160060201
    Abstract: Homochiral metal organic framework (MOF) selected from a group consisting of (Sp)-P5A-MOF-1 and (Rp)-P5A-MOF-1 is provided. The homochiral MOFs are prepared from pure enantiomer struts of formula (I): The homochiral MOFs are suitable for separation of enantiomers from racemic mixtures.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 3, 2016
    Inventors: James Fraser Stoddart, Nathan Strutt