Patents by Inventor Nathan Weyer Wright

Nathan Weyer Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for testing embedded memory on devices with multiple processor cores
    Patent number: 7155637
    Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: James Michael Jarboe, Jr., Nathan Weyer Wright, Nicholas Henry Schutt, Van Ho
  • Method and apparatus for testing embedded memory on devices with multiple processor cores
    Publication number: 20040153793
    Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.
    Type: Application
    Filed: April 29, 2003
    Publication date: August 5, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: James Michael Jarboe, Nathan Weyer Wright, Nicholas Henry Schutt, Van Ho