Abstract: A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.

Abstract: A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.

Abstract: A security integrated circuit is disclosed. In some embodiments, the security integrated circuit comprises metal configured memory that stores a first portion of each of a plurality of keys, programmable memory that stores a second portion of each of the plurality of keys, and an interface for connecting to an external authentication system. The metal configured memory and programmable memory store a prescribed finite number of host keys and matching device keys. In response to a received host key from the external authentication system, a matching device key is provided by the security integrated circuit.

Abstract: Various techniques for dynamic power FET switching are disclosed. In some embodiments, a device comprises an array of two or more independently switchable power MOSFETs that are configured to sense current in a high current mode and a low current mode as well as circuitry for automatically switching from the low current mode to the high current mode when sensed current is above a threshold to switch to the high current mode.