Patents by Inventor Nathaniel C. Berliner

Nathaniel C. Berliner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9018024
    Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Jason E. Cummings, Toshiharu Furukawa, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 8940554
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Toshiharu Furukawa, Douglas C. La Tulipe, Jr., William R. Tonti
  • Patent number: 8900973
    Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 2, 2014
    Assignees: International Business Machines Corporation, Globalfoundries Inc., Renesas Electronics America Inc., STMicroelectronics, Inc.
    Inventors: Nathaniel C. Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim, Toyoji Yamamoto, Zhengmao Zhu
  • Publication number: 20130052801
    Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS AMERICA, INC., GLOBALFOUNDRIES, STMICROELECTRONICS, INC.
    Inventors: Nathaniel C. Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim, Toyoji Yamamoto, Zhengmao Zhu
  • Publication number: 20120125538
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathaniel C. BERLINER, Kangguo CHENG, Toshiharu FURUKAWA, William R. TONTI, Douglas C. La TULIPE, JR.
  • Patent number: 8124427
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Toshiharu Furukawa, Douglas C. La Tulipe, Jr., William R. Tonti
  • Publication number: 20110095393
    Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Jason E. Cummings, Toshiharu Furukawa, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Publication number: 20110097824
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathaniel C. BERLINER, Kangguo CHENG, Toshiharu FURUKAWA, William R. TONTI, Douglas C. La TULIPE, Jr.