Patents by Inventor Nathaniel D. Hieter
Nathaniel D. Hieter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10970447Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: GrantFiled: June 3, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Patent number: 10552562Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: GrantFiled: November 20, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Patent number: 10540465Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: GrantFiled: March 26, 2019Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Publication number: 20190286773Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Publication number: 20190220561Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Patent number: 10216875Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: GrantFiled: February 23, 2017Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Patent number: 10210297Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: December 7, 2016Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20180239844Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: ApplicationFiled: November 20, 2017Publication date: August 23, 2018Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Publication number: 20180239843Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: ApplicationFiled: February 23, 2017Publication date: August 23, 2018Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Publication number: 20180239845Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.Type: ApplicationFiled: December 15, 2017Publication date: August 23, 2018Inventors: Nathaniel D. Hieter, Kerim Kalafala, Alexander J. Suess
-
Patent number: 9785735Abstract: A system and method perform global routing during integrated circuit fabrication. The method includes performing a design change in a portion of an integrated circuit design using a processor, determining whether the design change requires rerouting, and requesting a global routing lock based on determining that the design change requires the rerouting. The method also includes a router providing control of the global routing lock to one of two or more of the threads that request the global routing lock, and performing global routing for all of the two or more of the threads in parallel. A physical implementation of the integrated circuit design is obtained.Type: GrantFiled: October 11, 2016Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul M. Campbell, Nathaniel D. Hieter, Douglas Keller, Adam P. Matheny, Alexander J. Suess
-
Patent number: 9747400Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: December 7, 2016Date of Patent: August 29, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9703914Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: June 21, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9639654Abstract: Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.Type: GrantFiled: December 11, 2014Date of Patent: May 2, 2017Assignee: International Business Machines CorporationInventors: Bijian Chen, David J. Hathaway, Nathaniel D. Hieter, Kerim Kalafala, Jeffrey S. Piaget, Alexander J. Suess
-
Publication number: 20170083641Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20170083642Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20160300006Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: June 21, 2016Publication date: October 13, 2016Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20160283633Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9436791Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: March 24, 2015Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9418188Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: January 29, 2016Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess