Abstract: Embodiments are generally directed to determination of mobile display position and orientation using micropower impulse radar.

Abstract: Embodiments are generally directed to determination of mobile display position and orientation using micropower impulse radar.

Abstract: In embodiments, apparatuses, methods and storage media are described that are associated with synchronization of video during presentation. Video frames may be received by a computing device for display. A clock of a computing device may be used to control display of the frames as they are received. The clock may include a spread-spectrum clock. A clock control module may be configured to control a clock rate for the clock based on a comparison of times when frames of video are received and when frames of video are displayed. The clock control module may be configured to make adjustment calls to the clock of the computing device based on differences between the receipt times and the display times. The use of low-pass filtered differences being used as input into the clock control module may constitute a phase-locked loop. Other embodiments may be described and claimed.

Abstract: A method and an apparatus are provided for isolating faulty semiconductor devices in a multiple stream graphics system. The apparatus includes a buffer adapted to receive a plurality of data streams. The apparatus further includes a convolver comprising at least one convolution signature register; a router adapted to route the data streams from the buffer to the convolver, wherein the router comprises at least one router signature register; and an analyzer adapted to access the convolution and router signature registers, wherein the analyzer is capable of isolating at least one of a faulty semiconductor device and a faulty interconnection using the contents of the convolution and router signature registers.

Abstract: A method and an apparatus are provided for isolating faulty semiconductor devices in a multiple stream graphics system. The apparatus includes a buffer adapted to receive a plurality of data streams. The apparatus further includes a convolver comprising at least one convolution signature register; a router adapted to route the data streams from the buffer to the convolver, wherein the router comprises at least one router signature register; and an analyzer adapted to access the convolution and router signature registers, wherein the analyzer is capable of isolating at least one of a faulty semiconductor device and a faulty interconnection using the contents of the convolution and router signature registers.

Abstract: A video routing system including a plurality of video routers VR(0), VR(1), VR(NR−1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.

Abstract: A system and method for the phase alignment of signals of arbitrary relative frequency are described. A phase difference detector detects a phase difference between a first signal pulse and a corresponding second signal pulse. A phase comparator compares this detected phase difference to a calculated expected phase difference, to produce an error signal proportional to the difference. The clock generator adjusts the frequency of one of the signals by an amount based on the error signal, in order to phase align the first signal to the second signal. In a preferred embodiment, the first and second signals are video signals with a common frame rate and different line rates.

Abstract: A graphics system comprises a texture memory, a rendering engine, a sample buffer and a filtering engine. The rendering engine renders received primitives based on a render pixel array whose vertical and horizontal resolutions are dynamically programmable. The rendering engine determines render pixels that geometrically intersect a primitive. For each intersecting render pixel, a texture access may be required (if texture processing is turned on) to determine texture values. The texture values may be used to compute sample values at sample positions interior to the sample render pixel and the primitive. A controlling agent may decrease the vertical and horizontal resolutions of the render pixel array to control frame render time. The filtering engine may programmably generate virtual pixel centers covering the render pixel array. Any change in the render pixel resolutions may require an accommodating change in the virtual pixel array parameters.

Abstract: A programmable video output format (VOF) generator that enables a processing system to drive different video display devices with varying video format requirements. The programmable VOF generator includes a compiler that generates video formats based on user input, and a state machine that generates all video signals with requisite output format. The compiler allows the user to provide minimal information on general display parameters using a high-level language. Therefore, no specialized knowledge of the video display hardware requirements is required from the user.