Abstract: Systems, apparatuses, and methods for performing efficient video transmission are disclosed. In a video processing system, a transmitter identifies multiple planes in a scene. The transmitter renders and compresses each of the multiple planes with a combination of a corresponding compression level and a resolution, which is different from a combination of compression level and resolution of any other plane. For each plane, the transmitter inserts, in multi-plane information, data such as identification of the plane, a location in the video frame for the plane, and one or more of a resolution and compression level for the plane. The transmitter conveys the rendered and compressed planes along with the multi-plane information to a receiver. The receiver decodes each of the planes and insets each of the planes on any lower resolution planes of the multiple planes.

Abstract: A technique for adjusting the brightness values of images to be displayed on a stereoscopic head mounted display is provided herein. This technique improves the perceived dynamic range of the head mounted display by dynamically adjusting the pixel intensities (also known generally as “exposure”) of the images presented on the head mounted display based on a detected gaze direction. The head mounted display includes an eye tracker that is able to sense the gaze directions of the eyes. The eye tracker, head mounted display, or a processor of a computer system receives this information, determines an intersection point of the eye gaze and a screen within the head mounted display and identifies a gaze area around this intersection point. Using this gaze area, the processing system adjusts the pixel intensities of an image displayed on the screen based on the intensities of the pixels within the gaze area.

Abstract: Systems, apparatuses, and methods for performing efficient video compression are disclosed. A video processing system includes a transmitter sending a video stream over a wireless link to a receiver. The transmitter includes a processor and an encoder. The processor generates rendered blocks of pixels of a video frame, and when the processor predicts a compression level for a given region of the video frame is different from a compression level for immediately neighboring blocks, the processor generates side information. The side information identifies a location of the given region in the video frame and a type of content that causes the compression level differences. The processor sends the rendered video information and the side information as accompanying metadata to the encoder. The encoder updates encoding parameters based on the received side information, and compresses the rendered given region based on the updated encoding parameters.

Abstract: Systems, apparatuses, and methods for performing efficient video compression are disclosed. A video processing system includes a transmitter sending a video stream over a wireless link to a receiver. The transmitter includes a processor and an encoder. The processor generates rendered blocks of pixels of a video frame, and when the processor predicts a compression level for a given region of the video frame is different from a compression level for immediately neighboring blocks, the processor generates side information. The side information identifies a location of the given region in the video frame and a type of content that causes the compression level differences. The processor sends the rendered video information and the side information as accompanying metadata to the encoder. The encoder updates encoding parameters based on the received side information, and compresses the rendered given region based on the updated encoding parameters.

Abstract: Systems, apparatuses, and methods for performing efficient video transmission are disclosed. In a video processing system, a transmitter identifies multiple planes in a scene. The transmitter renders and compresses each of the multiple planes with a combination of a corresponding compression level and a resolution, which is different from a combination of compression level and resolution of any other plane. For each plane, the transmitter inserts, in multi-plane information, data such as identification of the plane, a location in the video frame for the plane, and one or more of a resolution and compression level for the plane. The transmitter conveys the rendered and compressed planes along with the multi-plane information to a receiver. The receiver decodes each of the planes and insets each of the planes on any lower resolution planes of the multiple planes.

Abstract: Systems, methods, and devices for generating an image frame for display to a user. Brain activity sensor data correlated with movement of a user is received. A predicted field of view of the user is determined based on the brain activity sensor data. An image frame is generated based on the predicted field of view. The image frame is transmitted to a display for display to a user. Some implementations provide for receiving and displaying a foveated image frame based on a predicted field of view of a user. Brain activity information of a user is captured. The brain activity information is communicated to a transceiver. The brain activity information is transmitted to a rendering device using the transceiver to generate a foveated image frame based on a predicted field of view of the user. The foveated image frame is received from the rendering device, decoded, and displayed to the user.

Abstract: Systems, methods, and devices for generating an image frame for display to a user. Brain activity sensor data correlated with movement of a user is received. A predicted field of view of the user is determined based on the brain activity sensor data. An image frame is generated based on the predicted field of view. The image frame is transmitted to a display for display to a user. Some implementations provide for receiving and displaying a foveated image frame based on a predicted field of view of a user. Brain activity information of a user is captured. The brain activity information is communicated to a transceiver. The brain activity information is transmitted to a rendering device using the transceiver to generate a foveated image frame based on a predicted field of view of the user. The foveated image frame is received from the rendering device, decoded, and displayed to the user.

Abstract: A technique for adjusting the brightness values of images to be displayed on a stereoscopic head mounted display is provided herein. This technique improves the perceived dynamic range of the head mounted display by dynamically adjusting the pixel intensities (also known generally as “exposure”) of the images presented on the head mounted display based on a detected gaze direction. The head mounted display includes an eye tracker that is able to sense the gaze directions of the eyes. The eye tracker, head mounted display, or a processor of a computer system receives this information, determines an intersection point of the eye gaze and a screen within the head mounted display and identifies a gaze area around this intersection point. Using this gaze area, the processing system adjusts the pixel intensities of an image displayed on the screen based on the intensities of the pixels within the gaze area.

Abstract: A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.

Abstract: A system for correcting the intensities of pixels supplied to a projector. An image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors. The system includes: a first unit configured to generate a horizontal scaling value; a second unit configured to generate a vertical scaling value; a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient, and a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel. The first unit and second unit compute their respective scaling values in a way that allows for regions whose boundaries non-aligned in the vertical direction.

Abstract: A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is responsible for a different interleaved region of screen space. Each chip performs part of the convolution process for a pixel and sends a partial result on to the next chip. The final chip completes the convolution and stores the filtered pixel. An alternate design interconnects chips in groups. The chips within a group operate in series, whereas the groups may operate in parallel.

Abstract: A computer system may include several integrated circuits and a routing circuit configured to route several data streams between the integrated circuits. The routing circuit includes several input ports, several output ports, and a signature analysis register coupled to one of the output ports. The signature analysis register is configured to collect data conveyed via the output port dependent upon whether the signature analysis register receives a tag identifying one of the plurality of data streams.

Abstract: A graphics system comprising a set of rendering processors and a series of filtering units. Each of the rendering processors couples to a corresponding one of the filtering units. Each rendering processor RP(K) is configured to (a) generate a stream of samples in response to received graphics primitives, (b) add a dither value DK to a data component of each the samples in the stream to obtain dithered data components, (c) buffer the dithered data components in an internal frame buffer, and (d) forward a truncated version of the dithered data components to the corresponding filtering unit. The filtering units are configured to perform a weighted averaging computation on the truncated dithered data components in a pipelined fashion to determine pixel data components.

Abstract: In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit may be connected to the first video format (Master) and generate an intermediate frequency. A second PLL circuit may use the intermediate frequency as the timebase for generating the pixel clock for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.

Abstract: A video routing system including a plurality of video routers VR(0), VR(1), . . . , VR(NR?1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.

Abstract: A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M1*M2)/(N1*N2). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.

Abstract: One embodiment of a method of frame detection may involve storing data indicative of a pulse duration and a number of successive occurrences of pulses having that pulse duration for each of several different pulse durations detected within a first field of a composite synchronization signal. This process may be repeated for one or more other fields of the composite synchronization signal. The data stored for each of the fields may be compared, and a frame signal may be generated dependent on an outcome of said comparing.

Abstract: A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.

Abstract: A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network and the memory of each rendering pipeline. The media processor in each rendering pipeline may direct the saving of state information of the corresponding rendering pipeline to the corresponding memory in response to receiving a corresponding context switch indication. A first of the media processors initiates the transfer of a resume token to the scheduling network through the corresponding rendering pipeline if the context switch occurs during an ordered processing mode. The scheduling network unblocks one or more rendering pipelines other than the first rendering pipeline in response to receiving the resume token.

Abstract: A system and method are disclosed to allow the tiling of sample jitter patterns to be independent of the tiling of clustered graphics accelerators. Each accelerator uses an x,y “bias” offset to shift the origin of the jitter pattern within the sample space region addressed by the accelerator. In this way, multiple accelerators may be programmed so that their jitter patterns integrate into one global pattern without discontinuities at the region boundaries.