Abstract: A power docking port system includes a charging probe having a substantially tetrahedral shape with multiple sides and a base portion, each of the multiple sides having a surface. A first set of contacts is embedded into the charging probe and each of the contacts extends radially outwardly from the base portion disposed at a predetermined angle from the others. A second set of contacts are individually mounted onto a different one of the multiple sides so as to conform with its surface. A port is adapted for use in current charging of electronic vehicles wherein the port is constructed to mate with the charging probe and the port includes a mating contact for each of the contacts on the charging probe. The port further includes an interface connector located at an output end of the port for electrically coupling with external power lines and other circuits.

Abstract: A power docking port system includes a charging probe having a substantially tetrahedral shape with multiple sides and a base portion, each of the multiple sides having a surface. A first set of contacts is embedded into the charging probe and each of the contacts extends radially outwardly from the base portion disposed at a predetermined angle from the others. A second set of contacts are individually mounted onto a different one of the multiple sides so as to conform with its surface. A port is adapted for use in current charging of electronic vehicles wherein the port is constructed to mate with the charging probe and the port includes a mating contact for each of the contacts on the charging probe. The port further includes an interface connector located at an output end of the port for electrically coupling with external power lines and other circuits.

Abstract: A method and apparatus for automatically loading device status information into a network device. One embodiment comprises an apparatus in a network device, wherein the network device enters a sleep state under particular conditions. In one embodiment, the apparatus is for communicating with other devices on the network and comprises control circuitry that controls communication between the network device and the other devices on the network. The apparatus further comprises a memory device that stores configuration data for the control circuitry, wherein at least a portion of the configuration data is loaded into the control circuitry upon initialization of the network device. The apparatus further comprises a buffer that stores keep-alive data that is transmitted to a plurality of the other devices in the network to refresh the presence of the network device in the network, wherein the keep-alive data is loaded into the buffer from the memory device upon initialization of the network device.

Abstract: A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.

Abstract: Low power event monitoring enabling logic allows wake up devices to maintain their proper functionality in the event of a momentary power loss, or in the event the operating system does not properly load upon power-up. The technology is particularly suited for use with network interface card supporting Wake-On-LAN functions. A component with low power enabling logic is provided for a system having power management resources responsive to power management event signals to switch to an operating state. The component comprises power logic having a first mode in which power consumption is limited to a first specified level and a second mode in which power consumption is limited to a second specified level higher than the first specified level. The component includes an interface to nonvolatile memory storing a control signal.

Abstract: An asynchronous switching circuit for multiple indeterminate bursting clocks. In one embodiment, the present invention recites a clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple clock inputs. The clock-switching circuit is comprised of a plurality of asynchronously-enabled clock circuits, a plurality of blocking circuits, a synchronizing clock, and a logic gate. Each of the plurality of blocking circuits has an input lead respectively coupled to one of the plurality of asynchronously-enabled clock circuits, each of the plurality of blocking circuits also has an output coupled to all of the plurality of asynchronously-enabled clock circuits except the one to which its input is coupled. The synchronizing clock is coupled to each of the plurality of blocking circuits while the logic gate is coupled to each of the plurality of asynchronously-enabled clock circuits.