Abstract: There is disclosed an automatic phasing network which network receives a data signal and synchronous timing signals. Initially, these signals are in an arbitrary but fixed phase relationship to one another. The circuit establishes a fixed phase relationship between the data and timing signals with a large degree of resistance of phase jitter. In order to accomplish these results, the circuit operates to select the edge of the clock signals which is farthest from given data transitions and uses this edge to produce a data signal which is synchronized to the timing signal. The circuit provides an accurate phase relationship between the data and timing signals for various out-of-phase conditions as where the data transitions lag the rising edge of the clock by angles which vary between -45 degrees to +315 degrees.