Patents by Inventor Nathaniel Peachey
Nathaniel Peachey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10461529Abstract: Aspects disclosed herein include trigger circuitry for electrostatic discharge (ESD) protection. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. Trigger circuitry, which includes a voltage divider for example, divides a voltage spike between a supply rail and a ground rail to provide a trigger voltage. An ESD clamping circuitry is activated to discharge the voltage spike when the trigger voltage is determined to exceed an ESD threshold voltage, thus protecting the IC from being damaged by the voltage spike. By activating the ESD clamping circuitry based on the trigger voltage divided from the voltage spike, it is possible to adapt the ESD protection circuit to provide ESD protection based on different ESD threshold voltages, thus making it possible to deploy the ESD protection circuit on ICs having different ESD protection requirements.Type: GrantFiled: March 24, 2016Date of Patent: October 29, 2019Assignee: Qorvo US, Inc.Inventors: Muhammad Iqbal Chaudhry, Nathaniel Peachey
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Patent number: 9997509Abstract: Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time.Type: GrantFiled: April 15, 2015Date of Patent: June 12, 2018Assignee: Qorvo US, Inc.Inventors: Muhammad Iqbal Chaudhry, Nathaniel Peachey
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Patent number: 9972999Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.Type: GrantFiled: August 6, 2015Date of Patent: May 15, 2018Assignee: Qorvo US, Inc.Inventor: Nathaniel Peachey
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Patent number: 9728532Abstract: An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.Type: GrantFiled: April 13, 2012Date of Patent: August 8, 2017Assignee: Qorvo US, Inc.Inventors: Swaminathan Muthukrishnan, Nathaniel Peachey, Cody Hale, Ralph Williamson
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Publication number: 20160352098Abstract: Aspects disclosed herein include trigger circuitry for electrostatic discharge (ESD) protection. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. Trigger circuitry, which includes a voltage divider for example, divides a voltage spike between a supply rail and a ground rail to provide a trigger voltage. An ESD clamping circuitry is activated to discharge the voltage spike when the trigger voltage is determined to exceed an ESD threshold voltage, thus protecting the IC from being damaged by the voltage spike. By activating the ESD clamping circuitry based on the trigger voltage divided from the voltage spike, it is possible to adapt the ESD protection circuit to provide ESD protection based on different ESD threshold voltages, thus making it possible to deploy the ESD protection circuit on ICs having different ESD protection requirements.Type: ApplicationFiled: March 24, 2016Publication date: December 1, 2016Inventors: Muhammad Iqbal Chaudhry, Nathaniel Peachey
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Publication number: 20160043542Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.Type: ApplicationFiled: August 6, 2015Publication date: February 11, 2016Inventor: Nathaniel Peachey
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Patent number: 9244478Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: GrantFiled: August 8, 2014Date of Patent: January 26, 2016Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Publication number: 20150325568Abstract: Aspects disclosed in the detailed description include an electrostatic discharge (ESD) protection circuit. In this regard, in one aspect, an ESD protection circuit is provided to protect an integrated circuit (IC) during fabrication and production. An ESD detection circuitry detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage. In response to detecting the ESD event, an ESD clamping circuitry is activated to discharge the ESD event, thus protecting the IC from being damaged by the ESD event. By detecting the ESD event based on the ESD threshold voltage, as opposed to detecting the ESD event based on rise time of the voltage spike, it is possible to prevent the ESD clamping circuitry from missing voltage spikes associated with a slow rise time or being falsely activated by a normal power-on voltage associated with a fast rise time.Type: ApplicationFiled: April 15, 2015Publication date: November 12, 2015Inventors: Muhammad Iqbal Chaudhry, Nathaniel Peachey
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Publication number: 20140347121Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Patent number: 8829981Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: GrantFiled: May 8, 2013Date of Patent: September 9, 2014Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Patent number: 8830767Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.Type: GrantFiled: June 28, 2013Date of Patent: September 9, 2014Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Joseph Hubert Colles, Jeffrey D. Potts
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Patent number: 8824217Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.Type: GrantFiled: June 28, 2013Date of Patent: September 2, 2014Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Joseph Hubert Colles, Jeffrey D. Potts
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Publication number: 20140091858Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.Type: ApplicationFiled: May 8, 2013Publication date: April 3, 2014Applicant: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Ralph Christopher Nieri
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Publication number: 20130286519Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Nathaniel Peachey, Joseph Hubert Colles, Jeffrey D. Potts
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Publication number: 20130286518Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Nathaniel Peachey, Joseph Hubert Colles, Jeffrey D. Potts
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Patent number: 8498166Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.Type: GrantFiled: October 27, 2010Date of Patent: July 30, 2013Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Joseph Hubert Colles, Jeffrey D. Potts
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Patent number: 8373956Abstract: A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.Type: GrantFiled: November 11, 2010Date of Patent: February 12, 2013Assignee: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Kiran V. Chatty, Chee Kwang Quek, Robert J. Gauthier, Jr., Nathaniel Peachey
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Publication number: 20120313173Abstract: Buried implants are used to reduce RF (radio-frequency) coupling in a SOI (Silicon-on-insulator) circuit. These buried implants are located above and/or below the BOX (buried oxide) layer of the SOI circuit. These buried implants may completely enclose the PWELL (P-type well) of an NFET (N-type Field Effect Transistor).Type: ApplicationFiled: June 7, 2012Publication date: December 13, 2012Applicant: RF MICRO DEVICES, INC.Inventors: Carl Dickey, Nathaniel Peachey, Robert Deuchars
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Publication number: 20120262828Abstract: An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.Type: ApplicationFiled: April 13, 2012Publication date: October 18, 2012Applicant: RF MICRO DEVICES, INC.Inventors: Swaminathan Muthukrishnan, Nathaniel Peachey, Cody Hale, Ralph Williamson
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Patent number: 7929263Abstract: The present invention is a latching electrostatic discharge (ESD) protection circuit that enables and latches an ESD clamping circuit upon an ESD event, and disables and un-latches the ESD clamping circuit upon either a drop in the DC supply voltage below a defined threshold or a time-out. The time-out protects against effects of inadvertent latching or any anomaly in which the latching ESD clamping circuit does not un-latch. An ESD event is a voltage spike between the DC supply voltage and ground wherein the ESD clamping circuit applies a low impedance between the DC supply voltage and ground to dissipate the energy contained in the voltage spike, thereby protecting adjacent circuitry.Type: GrantFiled: August 1, 2007Date of Patent: April 19, 2011Assignee: RF Micro Devices, Inc.Inventors: Nathaniel Peachey, Carlos Gamero