Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.

Abstract: Photonic integrated circuits required connection to germanium doped silica cored optical fibers or silica cored and fluorine doped silica cladding optical fibers which have low index contrast and large mode field diameters. However, the optical waveguide within a photonic integrated circuit such as formed using silicon-on-insulator or compound semiconductors tends to be high index contrast and small mode field diameter. Accordingly, it is necessary to implement adiabatic waveguide tapers with a high coupling efficiency and small footprint in order to couple into the photonic integrated circuits to/from the optical fiber. Prior art tapers have been generally high loss and absorb valuable die footprint. In contrast the inventors demonstrate a small low loss waveguide taper designed using a methodology they refer to a “constant loss”.

Abstract: Photonic integrated circuits required connection to germanium doped silica cored optical fibers or silica cored and fluorine doped silica cladding optical fibers which have low index contrast and large mode field diameters. However, the optical waveguide within a photonic integrated circuit such as formed using silicon-on-insulator or compound semiconductors tends to be high index contrast and small mode field diameter. Accordingly, it is necessary to implement adiabatic waveguide tapers with a high coupling efficiency and small footprint in order to couple into the photonic integrated circuits to/from the optical fiber. Prior art tapers have been generally high loss and absorb valuable die footprint. In contrast the inventors demonstrate a small low loss waveguide taper designed using a methodology they refer to a “constant loss.

Abstract: A method of growing high quality crystalline films on lattice-mismatched or amorphous layers is presented allowing semiconductor materials that would normally be subject to high stress and cracking to be employed allowing cost reductions and/or performance improvements in devices to be obtained. Catalysis of the growth of these films is based upon utilizing particular combinations of metals, materials, and structures to establish growth of the crystalline film from a predetermined location. The subsequent film growth occurring in one or two dimensions to cover a predetermined area of the amorphous or lattice-mismatched substrate. Accordingly the technique can be used to either cover a large area or provide tiles of crystalline material with or without crystalline film interconnections.

Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.

Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.

Abstract: An optical modulator includes a first layer that is transparent or semitransparent over a range of optical wavelengths; a modulation layer made from nanoparticles embedded in a matrix; a first electrode and a second electrode that create an electrical field that passes through the modulation layer. A method for forming a nanoparticle modulator includes obtaining and preparing a substrate; forming sub-layers on the substrate; forming a nanoparticle modulator layer, where the nanoparticle modulator layer is an electrical insulator and has a thickness of less than the wavelength of light the nanoparticle QCSE modulator is designed to modulate.

Abstract: A ridge waveguide with decreased optical losses from surface scattering includes a ridge waveguide with etched surfaces and an optical layer deposited on the ridge waveguide that substantially covers the etched surfaces. A method of reducing optical energy losses from scattering at etched surfaces of a ridge waveguide includes depositing a layer of optical material over the etched surfaces, the layer of optical material filling surface irregularities in the etched surfaces.

Abstract: An optical interconnect has a plurality of optical sources, a first lens configured to collimate optical beams from the plurality of optical sources, a second lens configured to refocus the optical beams, and a plurality of optical receivers configured to receive the refocused optical beams from the second lens.

Abstract: A method for making a multi-level nanowire structure includes establishing a first plurality of nanowires on a substrate surface, wherein at least some of the nanowires are i) aligned at a predetermined crystallographically defined angle with respect to the substrate surface, ii) aligned substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii. An insulating layer is established between the nanowires of the first plurality such that one of two opposed ends of at least some of the nanowires positioned i) at the predetermined crystallographically defined angle, ii) substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii is exposed. Regions are grown from each of the exposed ends, and such regions coalesce to form a substantially continuous layer on the insulating layer. A second plurality of nanowires is established on the substantially continuous layer.

Abstract: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer supports a surface plasmon that couples to the semiconductor junction by an evanescent field. Light is generated in a vicinity of the semiconductor junction and the surface plasmon is coupled to the semiconductor junction during light generation. The coupling enhances one or both of an efficiency of light emission and a light emission rate of the LED. A method of making the nanowire LED includes forming the nanowire, providing the insulating layer on the surface of the nanowire, and forming the shell layer on the insulating layer in the vicinity of the semiconductor junction.

Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.

Abstract: A method for forming a graphene layer is disclosed herein. The method includes establishing an insulating layer on a substrate such that at least one seed region, which exposes a surface of the substrate, is formed. A seed material in the seed region is exposed to a carbon-containing precursor gas, thereby initiating nucleation of the graphene layer on the seed material and enabling lateral growth of the graphene layer along at least a portion of a surface of the insulating layer.

Abstract: A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material.

Abstract: A semiconductor device which has controlled optical absorption includes a substrate, and a semiconductor layer supported by the substrate. The semiconductor has variable optical absorption at a predetermined optical frequency in relationship to a bandgap of the semiconductor layer. Also included is a strain application structure coupled to the semiconductor layer to create a strain in the semiconductor layer to change the semiconductor bandgap.

Abstract: A method of growing high quality crystalline films on lattice-mismatched or amorphous layers is presented allowing semiconductor materials that would normally be subject to high stress and cracking to be employed allowing cost reductions and/or performance improvements in devices to be obtained. Catalysis of the growth of these films is based upon utilizing particular combinations of metals, materials, and structures to establish growth of the crystalline film from a predetermined location. The subsequent film growth occurring in one or two dimensions to cover a predetermined area of the amorphous or lattice-mismatched substrate. Accordingly the technique can be used to either cover a large area or provide tiles of crystalline material with or without crystalline film interconnections.

Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.

Abstract: A method for making a multi-level nanowire structure includes establishing a first plurality of nanowires on a substrate surface, wherein at least some of the nanowires are i) aligned at a predetermined crystallographically defined angle with respect to the substrate surface, ii) aligned substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii. An insulating layer is established between the nanowires of the first plurality such that one of two opposed ends of at least some of the nanowires positioned i) at the predetermined crystallographically defined angle, ii) substantially perpendicular with respect to the substrate surface, or iii) combinations of i and ii is exposed. Regions are grown from each of the exposed ends, and such regions coalesce to form a substantially continuous layer on the insulating layer. A second plurality of nanowires is established on the substantially continuous layer.

Abstract: A method for forming a graphene layer is disclosed herein. The method includes establishing an insulating layer on a substrate such that at least one seed region, which exposes a surface of the substrate, is formed. A seed material in the seed region is exposed to a carbon-containing precursor gas, thereby initiating nucleation of the graphene layer on the seed material and enabling lateral growth of the graphene layer along at least a portion of a surface of the insulating layer.

Abstract: A structure includes a first amorphous layer and a second amorphous layer established on the first amorphous layer such that at least an edge of the first amorphous layer or the second amorphous having a predetermined geometry is exposed. A material having a controlled crystal orientation is selectively formed adjacent the exposed edge of the first amorphous layer or the second amorphous having the predetermined geometry.