Patents by Inventor Nathapong Suthiwongsunthorn
Nathapong Suthiwongsunthorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10381280Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: GrantFiled: April 3, 2017Date of Patent: August 13, 2019Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, John Ducyao Beleran, Serafin Padilla Pedron, Jr.
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Patent number: 10354934Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: April 24, 2018Date of Patent: July 16, 2019Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Publication number: 20180240726Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
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Patent number: 9978658Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: November 27, 2016Date of Patent: May 22, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Patent number: 9881863Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: February 8, 2017Date of Patent: January 30, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Patent number: 9842775Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.Type: GrantFiled: July 25, 2016Date of Patent: December 12, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Pandi C. Marimuthu, Shuangwu Huang, Nathapong Suthiwongsunthorn
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Publication number: 20170294401Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: ApplicationFiled: April 3, 2017Publication date: October 12, 2017Inventors: Nathapong SUTHIWONGSUNTHORN, John Ducyao BELERAN, Serafin Padilla PEDRON, JR.
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Patent number: 9741619Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: GrantFiled: January 9, 2017Date of Patent: August 22, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: William John Nelson, Nathapong Suthiwongsunthorn, Beng Yeung Ho, Poh Leng Wilson Ong
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Publication number: 20170148722Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio B. DIMAANO, JR., Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
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Publication number: 20170117185Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Inventors: William John NELSON, Nathapong SUTHIWONGSUNTHORN, Beng Yeung HO, Poh Leng Wilson ONG
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Patent number: 9613877Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: GrantFiled: October 10, 2013Date of Patent: April 4, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, John Ducyao Beleran, Serafin Padilla Pedron, Jr.
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Publication number: 20170077007Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: November 27, 2016Publication date: March 16, 2017Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
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Patent number: 9589875Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: September 9, 2015Date of Patent: March 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Patent number: 9583446Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.Type: GrantFiled: November 25, 2014Date of Patent: February 28, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Reza A. Pagaila, Byung Tai Do, Nathapong Suthiwongsunthorn
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Patent number: 9570314Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: GrantFiled: October 13, 2015Date of Patent: February 14, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: William John Nelson, Nathapong Suthiwongsunthorn, Beng Yeung Ho, Poh Leng Wilson Ong
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Patent number: 9508623Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: June 5, 2015Date of Patent: November 29, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
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Publication number: 20160336230Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Applicant: STATS ChipPAC Pte. Ltd.Inventors: Pandi C. Marimuthu, Shuangwu Huang, Nathapong Suthiwongsunthorn
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Patent number: 9472532Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.Type: GrantFiled: April 3, 2015Date of Patent: October 18, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Antonio Bambalan Dimaano, Jr., Nathapong Suthiwongsunthorn, Yong Bo Yang
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Patent number: 9443762Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.Type: GrantFiled: July 2, 2013Date of Patent: September 13, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Pandi C. Marimuthu, Shuangwu Huang, Nathapong Suthiwongsunthorn
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Publication number: 20160104626Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.Type: ApplicationFiled: October 13, 2015Publication date: April 14, 2016Inventors: William John NELSON, Nathapong SUTHIWONGSUNTHORN, Beng Yeung HO, Poh Leng Wilson ONG