Abstract: According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers.

Abstract: A level shift circuit of an embodiment includes: an input circuit configured to receive an input signal and connected to first and second power supply lines; first and second signal paths connected in parallel between the first power supply line and a third power supply line; first and second switching elements configured to control conduction of the first and second signal paths, respectively, based on the input signal; first and second diodes and a cross-coupled circuit arranged towards the third power supply line on the first and second signal paths; and an output circuit connected to the third power supply line and a fourth power supply line, and configured to output an output signal based on at least one of a signal appearing at a first node at one end of the first diode and a signal appearing at a second node at one end of the second diode.

Abstract: According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information.

Abstract: A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.

Abstract: A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.

Abstract: According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information.

Abstract: According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers.

Abstract: According to one embodiment, a test circuit comprises a function block, a test circuit, and a signal generation circuit. The test circuit is arranged in an area close to the function block having a plurality of transistors. The test circuit comprises a first flip-flop circuit, a second flip-flop circuit, and a logic circuit connected between the output of the first flip-flop circuit and the input of the second flip-flop circuit. The signal generation circuit generates clock pulses including a first clock pulse and a second clock pulse. The signal generation circuit is capable of controlling a pulse interval between the first clock pulse and the second clock pulse. In a test, the first flip-flop circuit outputs data in synchronization with the first clock pulse of the signal generation circuit and the second flip-flop circuit latches data in synchronization with the second clock pulse of the signal generation circuit.

Abstract: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.

Abstract: Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Abstract: A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the corresponding fuse to cause change in resistance with respect to the polysilicon fuses, a dummy fuse group including a plurality of dummy fuses having the same electrical properties as that of the polysilicon fuses, each dummy fuse having 1/n (n is an integer equal to or more than 1) times a resistance of the polysilicon fuses, a dummy transistor circuit which has at least one of dummy transistor having 1/n times a conductance of the programming transistors, a gate and a drain of the dummy transistor being connected to each other, and a current mirror circuit including the programming transistor and the dummy transistor, the current mirror circuit causing each polysi

Abstract: A driving circuit and a bus to transmit an output signal from the driving circuit are provided. The driving circuit includes a first P-channel transistor, a second P-channel transistor, an N-channel transistor and a capacitor. The first P-channel transistor includes a drain, a source to connect with a higher potential and a gate to receive a first input signal. The second P-channel transistor includes a drain connected to the bus, a source connected to the drain of the first P-channel transistor and a gate to receive a second input signal. The N-channel transistor includes a drain connected to the drain of the second P-channel transistor, a source to connect with a lower potential and a gate to receive the second input signal. The capacitor includes one end connected to the drain of the first P-channel transistor and another end to connect with the lower potential.

Abstract: A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90°, based on the phase difference signal, a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator, a sampling controller which performs phase interpolation of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal, and a sampling circuit which samples the embedded clock received by the receiver in synchronization with

Abstract: Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Abstract: A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.

Abstract: A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the corresponding fuse to cause change in resistance with respect to the polysilicon fuses, a dummy fuse group including a plurality of dummy fuses having the same electrical properties as that of the polysilicon fuses, each dummy fuse having 1/n (n is an integer equal to or more than 1) times a resistance of the polysilicon fuses, a dummy transistor circuit which has at least one of dummy transistor having 1/n times a conductance of the programming transistors, a gate and a drain of the dummy transistor being connected to each other, and a current mirror circuit including the programming transistor and the dummy transistor, the current mirror circuit causing each polysi

Abstract: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses programmed in accordance with identification information for specifying a chip mounting the cell array, a plurality of second fuses programmed in accordance with the redundancy information for replacing the defective memory cell with the redundancy cell and various setting information of the chip, a plurality of third fuses programmed in accordance with a CRC code generated based on the redundancy information, various setting information of the chip and the identification information, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of th

Abstract: A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.

Abstract: A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90°, based on the phase difference signal, a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator, a sampling controller which performs phase interpolation of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal, and a sampling circuit which samples the embedded clock received by the receiver in synchronization with

Abstract: A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.