Patents by Inventor Natsuki KUSUNO

Natsuki KUSUNO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10846231
    Abstract: To prevent an excessive increase of a dirty data amount in a cache memory. A processor acquires storage device information from each of storage devices. When receiving a write request to a first storage device group from a higher-level apparatus, the processor determines whether a write destination cache area corresponding to a write destination address indicated by the write request is reserved. When determining that the write destination cache area is not reserved, the processor performs, on the basis of the storage device information and cache information, reservation determination for determining whether to reserve the write destination cache area. When determining to reserve the write destination cache area, the processor reserves the write destination cache area. When determining not to reserve the write destination cache area, the processor stands by for the reservation of the write destination cache area.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: November 24, 2020
    Assignee: HITACHI, LTD.
    Inventors: Natsuki Kusuno, Toshiya Seki, Tomohiro Nishimoto, Takaki Matsushita
  • Publication number: 20180196755
    Abstract: To prevent an excessive increase of a dirty data amount in a cache memory. A processor acquires storage device information from each of storage devices. When receiving a write request to a first storage device group from a higher-level apparatus, the processor determines whether a write destination cache area corresponding to a write destination address indicated by the write request is reserved. When determining that the write destination cache area is not reserved, the processor performs, on the basis of the storage device information and cache information, reservation determination for determining whether to reserve the write destination cache area. When determining to reserve the write destination cache area, the processor reserves the write destination cache area. When determining not to reserve the write destination cache area, the processor stands by for the reservation of the write destination cache area.
    Type: Application
    Filed: November 13, 2015
    Publication date: July 12, 2018
    Applicant: HITACHI, LTD.
    Inventors: Natsuki KUSUNO, Toshiya SEKI, Tomohiro NISHIMOTO, Takaki MATSUSHITA